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llvm-mirror/test/CodeGen/X86/avx512-arith.ll

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[x86] Remove some of the --show-mc-encoding flags from avx512 tests that need to be updated for the new vector shuffle lowering. After talking to Adam Nemet, Tim Northover, etc., it seems that testing MC encodings in the same suite as the basic codegen isn't the right approach. Instead, we're going to want dedicated MC tests for the encodings. These encodings are starting to get in my way so I wanted to cut them out early. The total set of instructions that should have encoding tests added is: vpaddd vsqrtss vsqrtsd vmovlhps vmovhlps valignq vbroadcastss Not too many parts of these tests were even using this. =] llvm-svn: 218932
2014-10-03 02:36:29 +02:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
define <8 x double> @addpd512(<8 x double> %y, <8 x double> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: addpd512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vaddpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%add.i = fadd <8 x double> %x, %y
ret <8 x double> %add.i
}
define <8 x double> @addpd512fold(<8 x double> %y) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: addpd512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vaddpd {{.*}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%add.i = fadd <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.800000e+00, double 2.300000e+00, double 1.200000e+00>
ret <8 x double> %add.i
}
define <16 x float> @addps512(<16 x float> %y, <16 x float> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: addps512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%add.i = fadd <16 x float> %x, %y
ret <16 x float> %add.i
}
define <16 x float> @addps512fold(<16 x float> %y) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: addps512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vaddps {{.*}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%add.i = fadd <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 4.500000e+00, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
ret <16 x float> %add.i
}
define <8 x double> @subpd512(<8 x double> %y, <8 x double> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: subpd512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vsubpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%sub.i = fsub <8 x double> %x, %y
ret <8 x double> %sub.i
}
define <8 x double> @subpd512fold(<8 x double> %y, <8 x double>* %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: subpd512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vsubpd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%tmp2 = load <8 x double>* %x, align 8
%sub.i = fsub <8 x double> %y, %tmp2
ret <8 x double> %sub.i
}
define <16 x float> @subps512(<16 x float> %y, <16 x float> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: subps512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vsubps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%sub.i = fsub <16 x float> %x, %y
ret <16 x float> %sub.i
}
define <16 x float> @subps512fold(<16 x float> %y, <16 x float>* %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: subps512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vsubps (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%tmp2 = load <16 x float>* %x, align 4
%sub.i = fsub <16 x float> %y, %tmp2
ret <16 x float> %sub.i
}
AVX-512: MUL operation lowering for v8i64 llvm-svn: 193083
2013-10-21 15:27:34 +02:00
define <8 x i64> @imulq512(<8 x i64> %y, <8 x i64> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: imulq512:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmuludq %zmm0, %zmm1, %zmm2
; CHECK-NEXT: vpsrlq $32, %zmm0, %zmm3
; CHECK-NEXT: vpmuludq %zmm3, %zmm1, %zmm3
; CHECK-NEXT: vpsllq $32, %zmm3, %zmm3
; CHECK-NEXT: vpaddq %zmm3, %zmm2, %zmm2
; CHECK-NEXT: vpsrlq $32, %zmm1, %zmm1
; CHECK-NEXT: vpmuludq %zmm0, %zmm1, %zmm0
; CHECK-NEXT: vpsllq $32, %zmm0, %zmm0
; CHECK-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; CHECK-NEXT: retq
AVX-512: MUL operation lowering for v8i64 llvm-svn: 193083
2013-10-21 15:27:34 +02:00
%z = mul <8 x i64>%x, %y
ret <8 x i64>%z
}
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
define <8 x double> @mulpd512(<8 x double> %y, <8 x double> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: mulpd512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vmulpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%mul.i = fmul <8 x double> %x, %y
ret <8 x double> %mul.i
}
define <8 x double> @mulpd512fold(<8 x double> %y) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: mulpd512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vmulpd {{.*}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%mul.i = fmul <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
ret <8 x double> %mul.i
}
define <16 x float> @mulps512(<16 x float> %y, <16 x float> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: mulps512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vmulps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%mul.i = fmul <16 x float> %x, %y
ret <16 x float> %mul.i
}
define <16 x float> @mulps512fold(<16 x float> %y) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: mulps512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vmulps {{.*}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%mul.i = fmul <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
ret <16 x float> %mul.i
}
define <8 x double> @divpd512(<8 x double> %y, <8 x double> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: divpd512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vdivpd %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%div.i = fdiv <8 x double> %x, %y
ret <8 x double> %div.i
}
define <8 x double> @divpd512fold(<8 x double> %y) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: divpd512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vdivpd {{.*}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%div.i = fdiv <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
ret <8 x double> %div.i
}
define <16 x float> @divps512(<16 x float> %y, <16 x float> %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: divps512:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vdivps %zmm0, %zmm1, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%div.i = fdiv <16 x float> %x, %y
ret <16 x float> %div.i
}
define <16 x float> @divps512fold(<16 x float> %y) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: divps512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vdivps {{.*}}(%rip), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%div.i = fdiv <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000>
ret <16 x float> %div.i
}
define <8 x i64> @vpaddq_test(<8 x i64> %i, <8 x i64> %j) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddq_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%x = add <8 x i64> %i, %j
ret <8 x i64> %x
}
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
define <8 x i64> @vpaddq_fold_test(<8 x i64> %i, <8 x i64>* %j) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddq_fold_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%tmp = load <8 x i64>* %j, align 4
%x = add <8 x i64> %i, %tmp
ret <8 x i64> %x
}
define <8 x i64> @vpaddq_broadcast_test(<8 x i64> %i) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddq_broadcast_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%x = add <8 x i64> %i, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
ret <8 x i64> %x
}
define <8 x i64> @vpaddq_broadcast2_test(<8 x i64> %i, i64* %j) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddq_broadcast2_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq (%rdi){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%tmp = load i64* %j
%j.0 = insertelement <8 x i64> undef, i64 %tmp, i32 0
%j.1 = insertelement <8 x i64> %j.0, i64 %tmp, i32 1
%j.2 = insertelement <8 x i64> %j.1, i64 %tmp, i32 2
%j.3 = insertelement <8 x i64> %j.2, i64 %tmp, i32 3
%j.4 = insertelement <8 x i64> %j.3, i64 %tmp, i32 4
%j.5 = insertelement <8 x i64> %j.4, i64 %tmp, i32 5
%j.6 = insertelement <8 x i64> %j.5, i64 %tmp, i32 6
%j.7 = insertelement <8 x i64> %j.6, i64 %tmp, i32 7
%x = add <8 x i64> %i, %j.7
ret <8 x i64> %x
}
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
define <16 x i32> @vpaddd_test(<16 x i32> %i, <16 x i32> %j) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%x = add <16 x i32> %i, %j
ret <16 x i32> %x
}
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
define <16 x i32> @vpaddd_fold_test(<16 x i32> %i, <16 x i32>* %j) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_fold_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%tmp = load <16 x i32>* %j, align 4
%x = add <16 x i32> %i, %tmp
ret <16 x i32> %x
}
define <16 x i32> @vpaddd_broadcast_test(<16 x i32> %i) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_broadcast_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%x = add <16 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
ret <16 x i32> %x
}
define <16 x i32> @vpaddd_mask_test(<16 x i32> %i, <16 x i32> %j, <16 x i32> %mask1) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_mask_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm3, %zmm3, %zmm3
; CHECK-NEXT: vpcmpneqd %zmm3, %zmm2, %k1
; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = add <16 x i32> %i, %j
%r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i
ret <16 x i32> %r
}
define <16 x i32> @vpaddd_maskz_test(<16 x i32> %i, <16 x i32> %j, <16 x i32> %mask1) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_maskz_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm3, %zmm3, %zmm3
; CHECK-NEXT: vpcmpneqd %zmm3, %zmm2, %k1
; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = add <16 x i32> %i, %j
%r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
ret <16 x i32> %r
}
define <16 x i32> @vpaddd_mask_fold_test(<16 x i32> %i, <16 x i32>* %j.ptr, <16 x i32> %mask1) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_mask_fold_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm2, %zmm2, %zmm2
; CHECK-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; CHECK-NEXT: vpaddd (%rdi), %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%j = load <16 x i32>* %j.ptr
%x = add <16 x i32> %i, %j
%r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i
ret <16 x i32> %r
}
define <16 x i32> @vpaddd_mask_broadcast_test(<16 x i32> %i, <16 x i32> %mask1) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_mask_broadcast_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm2, %zmm2, %zmm2
; CHECK-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 {%k1}
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = add <16 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> %i
ret <16 x i32> %r
}
define <16 x i32> @vpaddd_maskz_fold_test(<16 x i32> %i, <16 x i32>* %j.ptr, <16 x i32> %mask1) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_maskz_fold_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm2, %zmm2, %zmm2
; CHECK-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; CHECK-NEXT: vpaddd (%rdi), %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%j = load <16 x i32>* %j.ptr
%x = add <16 x i32> %i, %j
%r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
ret <16 x i32> %r
}
define <16 x i32> @vpaddd_maskz_broadcast_test(<16 x i32> %i, <16 x i32> %mask1) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpaddd_maskz_broadcast_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpxord %zmm2, %zmm2, %zmm2
; CHECK-NEXT: vpcmpneqd %zmm2, %zmm1, %k1
; CHECK-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 {%k1} {z}
; CHECK-NEXT: retq
AVX-512: Implemented masking for integer arithmetic & logic instructions. By Robert Khasanov rob.khasanov@gmail.com llvm-svn: 204906
2014-03-27 10:45:08 +01:00
%mask = icmp ne <16 x i32> %mask1, zeroinitializer
%x = add <16 x i32> %i, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%r = select <16 x i1> %mask, <16 x i32> %x, <16 x i32> zeroinitializer
ret <16 x i32> %r
}
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
define <8 x i64> @vpsubq_test(<8 x i64> %i, <8 x i64> %j) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpsubq_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsubq %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%x = sub <8 x i64> %i, %j
ret <8 x i64> %x
}
define <16 x i32> @vpsubd_test(<16 x i32> %i, <16 x i32> %j) nounwind readnone {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpsubd_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpsubd %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%x = sub <16 x i32> %i, %j
ret <16 x i32> %x
}
define <16 x i32> @vpmulld_test(<16 x i32> %i, <16 x i32> %j) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: vpmulld_test:
; CHECK: ## BB#0:
; CHECK-NEXT: vpmulld %zmm1, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%x = mul <16 x i32> %i, %j
ret <16 x i32> %x
}
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS llvm-svn: 189472
2013-08-28 13:21:58 +02:00
declare float @sqrtf(float) readnone
define float @sqrtA(float %a) nounwind uwtable readnone ssp {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: sqrtA:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: retq
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS llvm-svn: 189472
2013-08-28 13:21:58 +02:00
entry:
%conv1 = tail call float @sqrtf(float %a) nounwind readnone
ret float %conv1
}
declare double @sqrt(double) readnone
define double @sqrtB(double %a) nounwind uwtable readnone ssp {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: sqrtB:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: retq
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS llvm-svn: 189472
2013-08-28 13:21:58 +02:00
entry:
%call = tail call double @sqrt(double %a) nounwind readnone
ret double %call
}
declare float @llvm.sqrt.f32(float)
define float @sqrtC(float %a) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: sqrtC:
; CHECK: ## BB#0:
; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: retq
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS llvm-svn: 189472
2013-08-28 13:21:58 +02:00
%b = call float @llvm.sqrt.f32(float %a)
ret float %b
}
Fix AVX512 vector sqrt assembly strings. llvm-svn: 201681
2014-02-19 16:16:09 +01:00
declare <16 x float> @llvm.sqrt.v16f32(<16 x float>)
define <16 x float> @sqrtD(<16 x float> %a) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: sqrtD:
; CHECK: ## BB#0:
; CHECK-NEXT: vsqrtps %zmm0, %zmm0
; CHECK-NEXT: retq
Fix AVX512 vector sqrt assembly strings. llvm-svn: 201681
2014-02-19 16:16:09 +01:00
%b = call <16 x float> @llvm.sqrt.v16f32(<16 x float> %a)
ret <16 x float> %b
}
declare <8 x double> @llvm.sqrt.v8f64(<8 x double>)
define <8 x double> @sqrtE(<8 x double> %a) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: sqrtE:
; CHECK: ## BB#0:
; CHECK-NEXT: vsqrtpd %zmm0, %zmm0
; CHECK-NEXT: retq
Fix AVX512 vector sqrt assembly strings. llvm-svn: 201681
2014-02-19 16:16:09 +01:00
%b = call <8 x double> @llvm.sqrt.v8f64(<8 x double> %a)
ret <8 x double> %b
}
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS llvm-svn: 189472
2013-08-28 13:21:58 +02:00
define <16 x float> @fadd_broadcast(<16 x float> %a) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: fadd_broadcast:
; CHECK: ## BB#0:
; CHECK-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS llvm-svn: 189472
2013-08-28 13:21:58 +02:00
%b = fadd <16 x float> %a, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
ret <16 x float> %b
}
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
define <8 x i64> @addq_broadcast(<8 x i64> %a) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: addq_broadcast:
; CHECK: ## BB#0:
; CHECK-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%b = add <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %b
}
define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: orq_broadcast:
; CHECK: ## BB#0:
; CHECK-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
%b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
ret <8 x i64> %b
}
define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: andd512fold:
; CHECK: ## BB#0: ## %entry
; CHECK-NEXT: vpandd (%rdi), %zmm0, %zmm0
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%a = load <16 x i32>* %x, align 4
%b = and <16 x i32> %y, %a
ret <16 x i32> %b
}
define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-LABEL: andqbrst:
; CHECK: ## BB#0: ## %entry
[x86] Enable the new vector shuffle lowering by default. Update the entire regression test suite for the new shuffles. Remove most of the old testing which was devoted to the old shuffle lowering path and is no longer relevant really. Also remove a few other random tests that only really exercised shuffles and only incidently or without any interesting aspects to them. Benchmarking that I have done shows a few small regressions with this on LNT, zero measurable regressions on real, large applications, and for several benchmarks where the loop vectorizer fires in the hot path it shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy Bridge machines. Running on AMD machines shows even more dramatic improvements. When using newer ISA vector extensions the gains are much more modest, but the code is still better on the whole. There are a few regressions being tracked (PR21137, PR21138, PR21139) but by and large this is expected to be a win for x86 generated code performance. It is also more correct than the code it replaces. I have fuzz tested this extensively with ISA extensions up through AVX2 and found no crashes or miscompiles (yet...). The old lowering had a few miscompiles and crashers after a somewhat smaller amount of fuzz testing. There is one significant area where the new code path lags behind and that is in AVX-512 support. However, there was *extremely little* support for that already and so this isn't a significant step backwards and the new framework will probably make it easier to implement lowering that uses the full power of AVX-512's table-based shuffle+blend (IMO). Many thanks to Quentin, Andrea, Robert, and others for benchmarking assistance. Thanks to Adam and others for help with AVX-512. Thanks to Hal, Eric, and *many* others for answering my incessant questions about how the backend actually works. =] I will leave the old code path in the tree until the 3 PRs above are at least resolved to folks' satisfaction. Then I will rip it (and 1000s of lines of code) out. =] I don't expect this flag to stay around for very long. It may not survive next week. llvm-svn: 219046
2014-10-04 05:52:55 +02:00
; CHECK-NEXT: vmovq (%rdi), %xmm1
; CHECK-NEXT: vpbroadcastq %xmm1, %ymm1
; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
[x86] Regenerate an avx512 test with my script to provide a nice baseline for updates from the new vector shuffle lowering. I've inspected the results here, and I couldn't find any register allocation decisions where there should be any realistic way to register allocate things differently. The closest was the imul test case. If you see something here you'd like register number variables on, just shout and I'll add them. llvm-svn: 218935
2014-10-03 02:44:46 +02:00
; CHECK-NEXT: retq
AVX-512: added arithmetic and logical operations. ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
2013-08-19 15:26:14 +02:00
entry:
%a = load i64* %ap, align 8
%b = insertelement <8 x i64> undef, i64 %a, i32 0
%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
%d = and <8 x i64> %p1, %c
ret <8 x i64>%d
AVX-512: MUL operation lowering for v8i64 llvm-svn: 193083
2013-10-21 15:27:34 +02:00
}
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