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llvm-mirror/test/MC/VE/ST.s

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[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: st %s11, 32767
# CHECK-ENCODING: encoding: [0xff,0x7f,0x00,0x00,0x00,0x00,0x0b,0x11]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
st %s11, 32767
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: st %s11, 20(%s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x11]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
st %s11, 20(%s11)
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: st %s11, -1(, %s11)
# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x11]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
st %s11, -1(, %s11)
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: st %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x11]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
st %s11, 20(%s10, %s11)
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: stu %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x12]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
stu %s11, 20(%s10, %s11)
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: stl %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x13]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
stl %s11, 20(%s10, %s11)
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: st2b %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x14]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
st2b %s11, 20(%s10, %s11)
[VE] Support a basic disassembler for Aurora VE target Summary: Add a basic disassember and regression tests of LEA/LD/ST instructions. This patch also removes DecoderMethod declarations for branch and call since those are not implemented in this patch. They will be added again later. This patch also corrects DecoderMethod for LD/ST instructions for one byte or two. Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:32 +02:00
# CHECK-INST: st1b %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x15]
[VE] Support I32/F32 registers in assembler parser Summary: Support I32/F32 registers in assembler parser and add regression tests of LD/ST instructions. Differential Revision: https://reviews.llvm.org/D80777
2020-06-02 10:22:30 +02:00
st1b %s11, 20(%s10, %s11)
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