RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity
e3b57c8a21
llvm-mirror/test/MC/Sparc/sparc-fp-instructions.s

157 lines
7.1 KiB
ArmAsm
Raw Normal View History

[Sparc] Add support for parsing floating point instructions. llvm-svn: 199033
2014-01-12 05:48:54 +01:00
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80]
! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00]
! CHECK: fitoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x80]
fitos %f0, %f4
fitod %f0, %f4
fitoq %f0, %f4
! CHECK: fstoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x20]
! CHECK: fdtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x40]
! CHECK: fqtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x60]
fstoi %f0, %f4
fdtoi %f0, %f4
fqtoi %f0, %f4
! CHECK: fstod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x20]
! CHECK: fstoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0xa0]
fstod %f0, %f4
fstoq %f0, %f4
! CHECK: fdtos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0xc0]
! CHECK: fdtoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0xc0]
fdtos %f0, %f4
fdtoq %f0, %f4
! CHECK: fqtos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0xe0]
! CHECK: fqtod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x60]
fqtos %f0, %f4
fqtod %f0, %f4
! CHECK: fmovs %f0, %f4 ! encoding: [0x89,0xa0,0x00,0x20]
! CHECK: fmovd %f0, %f4 ! encoding: [0x89,0xa0,0x00,0x40]
! CHECK: fmovq %f0, %f4 ! encoding: [0x89,0xa0,0x00,0x60]
fmovs %f0, %f4
fmovd %f0, %f4
fmovq %f0, %f4
! CHECK: fnegs %f0, %f4 ! encoding: [0x89,0xa0,0x00,0xa0]
! CHECK: fnegd %f0, %f4 ! encoding: [0x89,0xa0,0x00,0xc0]
! CHECK: fnegq %f0, %f4 ! encoding: [0x89,0xa0,0x00,0xe0]
fnegs %f0, %f4
fnegd %f0, %f4
fnegq %f0, %f4
! CHECK: fabss %f0, %f4 ! encoding: [0x89,0xa0,0x01,0x20]
! CHECK: fabsd %f0, %f4 ! encoding: [0x89,0xa0,0x01,0x40]
! CHECK: fabsq %f0, %f4 ! encoding: [0x89,0xa0,0x01,0x60]
fabss %f0, %f4
fabsd %f0, %f4
fabsq %f0, %f4
! CHECK: fsqrts %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x20]
! CHECK: fsqrtd %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x40]
! CHECK: fsqrtq %f0, %f4 ! encoding: [0x89,0xa0,0x05,0x60]
fsqrts %f0, %f4
fsqrtd %f0, %f4
fsqrtq %f0, %f4
! CHECK: fadds %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0x24]
! CHECK: faddd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0x44]
! CHECK: faddq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0x64]
fadds %f0, %f4, %f8
faddd %f0, %f4, %f8
faddq %f0, %f4, %f8
[Sparc] Correct quad register list in the asm parser. Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
2014-01-24 06:24:01 +01:00
! make sure we can handle V9 double registers and their aliased quad registers.
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
2016-02-27 13:49:59 +01:00
! CHECK: faddd %f32, %f34, %f62 ! encoding: [0xbf,0xa0,0x48,0x43]
! CHECK: faddq %f32, %f36, %f60 ! encoding: [0xbb,0xa0,0x48,0x65]
[Sparc] Correct quad register list in the asm parser. Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
2014-01-24 06:24:01 +01:00
faddd %f32, %f34, %f62
faddq %f32, %f36, %f60
[Sparc] Add support for parsing floating point instructions. llvm-svn: 199033
2014-01-12 05:48:54 +01:00
! CHECK: fsubs %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xa4]
! CHECK: fsubd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xc4]
! CHECK: fsubq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x08,0xe4]
fsubs %f0, %f4, %f8
fsubd %f0, %f4, %f8
fsubq %f0, %f4, %f8
! CHECK: fmuls %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x24]
! CHECK: fmuld %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x44]
! CHECK: fmulq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0x64]
fmuls %f0, %f4, %f8
fmuld %f0, %f4, %f8
fmulq %f0, %f4, %f8
! CHECK: fsmuld %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x0d,0x24]
! CHECK: fdmulq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x0d,0xc4]
fsmuld %f0, %f4, %f8
fdmulq %f0, %f4, %f8
! CHECK: fdivs %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0xa4]
! CHECK: fdivd %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0xc4]
! CHECK: fdivq %f0, %f4, %f8 ! encoding: [0x91,0xa0,0x09,0xe4]
fdivs %f0, %f4, %f8
fdivd %f0, %f4, %f8
fdivq %f0, %f4, %f8
TableGen: fix operand counting for aliases TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
2014-05-16 11:42:04 +02:00
! CHECK: fcmps %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24]
! CHECK: fcmpd %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44]
! CHECK: fcmpq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64]
[Sparc] Add support for parsing floating point instructions. llvm-svn: 199033
2014-01-12 05:48:54 +01:00
fcmps %f0, %f4
fcmpd %f0, %f4
fcmpq %f0, %f4
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
2016-02-27 13:49:59 +01:00
! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
[Sparc] Add fcmpe* instructions to Sparc backend. llvm-svn: 202661
2014-03-02 20:56:19 +01:00
fcmpes %f0, %f4
fcmped %f0, %f4
fcmpeq %f0, %f4
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
2016-02-27 13:49:59 +01:00
! CHECK: fcmps %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x24]
! CHECK: fcmpd %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x44]
! CHECK: fcmpq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0x64]
[Sparc] Add support for parsing fcmp with %fcc registers. llvm-svn: 202610
2014-03-02 04:39:39 +01:00
fcmps %fcc2, %f0, %f4
fcmpd %fcc2, %f0, %f4
fcmpq %fcc2, %f0, %f4
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
2016-02-27 13:49:59 +01:00
! CHECK: fcmpes %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xa4]
! CHECK: fcmped %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xc4]
! CHECK: fcmpeq %fcc2, %f0, %f4 ! encoding: [0x85,0xa8,0x0a,0xe4]
[Sparc] Add fcmpe* instructions to Sparc backend. llvm-svn: 202661
2014-03-02 20:56:19 +01:00
fcmpes %fcc2, %f0, %f4
fcmped %fcc2, %f0, %f4
fcmpeq %fcc2, %f0, %f4
[Sparc] Add support for parsing floating point instructions. llvm-svn: 199033
2014-01-12 05:48:54 +01:00
! CHECK: fxtos %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x80]
! CHECK: fxtod %f0, %f4 ! encoding: [0x89,0xa0,0x11,0x00]
! CHECK: fxtoq %f0, %f4 ! encoding: [0x89,0xa0,0x11,0x80]
fxtos %f0, %f4
fxtod %f0, %f4
fxtoq %f0, %f4
! CHECK: fstox %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x20]
! CHECK: fdtox %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x40]
! CHECK: fqtox %f0, %f4 ! encoding: [0x89,0xa0,0x10,0x60]
fstox %f0, %f4
fdtox %f0, %f4
fqtox %f0, %f4
Load/store for float registers from/to alternate space. llvm-svn: 244532
2015-08-11 01:33:17 +02:00
! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00]
! CHECK: ldd [%l0], %f48 ! encoding: [0xe3,0x1c,0x00,0x00]
Load/store instructions for floating points with address space require SparcV9. To properly handle this, define the *a instructions as separate instruction classes by refactoring the LoadA and StoreA multiclasses. Move the instruction tests into the sparcv9 file to test the difference. llvm-svn: 245360
2015-08-18 23:31:46 +02:00
ld [%l0], %f29
Load/store for float registers from/to alternate space. llvm-svn: 244532
2015-08-11 01:33:17 +02:00
ldd [%l0], %f48
! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00]
! CHECK: std %f48, [%l0] ! encoding: [0xe3,0x3c,0x00,0x00]
Load/store instructions for floating points with address space require SparcV9. To properly handle this, define the *a instructions as separate instruction classes by refactoring the LoadA and StoreA multiclasses. Move the instruction tests into the sparcv9 file to test the difference. llvm-svn: 245360
2015-08-18 23:31:46 +02:00
st %f29, [%l0]
Load/store for float registers from/to alternate space. llvm-svn: 244532
2015-08-11 01:33:17 +02:00
std %f48, [%l0]
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133
2016-02-27 13:49:59 +01:00
! CHECK: std %fq, [%o4] ! encoding: [0xc1,0x33,0x00,0x00]
! CHECK: std %fq, [%l1+62] ! encoding: [0xc1,0x34,0x60,0x3e]
! CHECK: std %fq, [%i3+%l7] ! encoding: [0xc1,0x36,0xc0,0x17]
std %fq, [%o4]
std %fq, [%l1+62]
std %fq, [%i3+%l7]
Reference in New Issue Copy Permalink