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llvm-mirror/test/CodeGen/X86/vec_insert-7.ll

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Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else. llvm-svn: 115352
2010-10-01 23:39:35 +02:00
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=i686-apple-darwin9 | FileCheck %s
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
; MMX insertelement is not available; these are promoted to XMM.
; (Without SSE they are split to two ints, and the code is much better.)
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code. Also commit Mon Ping's VSETCC patch llvm-svn: 54039
2008-07-25 21:05:58 +02:00
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code. Also commit Mon Ping's VSETCC patch llvm-svn: 54039
2008-07-25 21:05:58 +02:00
entry:
We must check for something. llvm-svn: 115309
2010-10-01 12:20:10 +02:00
; CHECK: mmx_movzl
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else. llvm-svn: 115352
2010-10-01 23:39:35 +02:00
; CHECK: pinsrd
; CHECK: pinsrd
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
%tmp = bitcast x86_mmx %x to <2 x i32>
%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0 ; <<2 x i32>> [#uses=1]
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code. Also commit Mon Ping's VSETCC patch llvm-svn: 54039
2008-07-25 21:05:58 +02:00
%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1 ; <<2 x i32>> [#uses=1]
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
%tmp9 = bitcast <2 x i32> %tmp8 to x86_mmx
ret x86_mmx %tmp9
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code. Also commit Mon Ping's VSETCC patch llvm-svn: 54039
2008-07-25 21:05:58 +02:00
}
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