2019-09-10 12:39:09 +02:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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@zeroEqualityTest01.buffer1 = private unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 4], align 4
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@zeroEqualityTest01.buffer2 = private unnamed_addr constant [3 x i32] [i32 1, i32 2, i32 3], align 4
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@zeroEqualityTest02.buffer1 = private unnamed_addr constant [4 x i32] [i32 4, i32 0, i32 0, i32 0], align 4
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@zeroEqualityTest02.buffer2 = private unnamed_addr constant [4 x i32] [i32 3, i32 0, i32 0, i32 0], align 4
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@zeroEqualityTest03.buffer1 = private unnamed_addr constant [4 x i32] [i32 0, i32 0, i32 0, i32 3], align 4
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@zeroEqualityTest03.buffer2 = private unnamed_addr constant [4 x i32] [i32 0, i32 0, i32 0, i32 4], align 4
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@zeroEqualityTest04.buffer1 = private unnamed_addr constant [15 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14], align 4
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@zeroEqualityTest04.buffer2 = private unnamed_addr constant [15 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 13], align 4
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declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64) local_unnamed_addr #1
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; Check 4 bytes - requires 1 load for each param.
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define signext i32 @zeroEqualityTest02(i8* %x, i8* %y) {
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; CHECK-LABEL: zeroEqualityTest02:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: lwz 4, 0(4)
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; CHECK-NEXT: xor 3, 3, 4
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: xori 3, 3, 1
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 4)
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%not.cmp = icmp ne i32 %call, 0
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%. = zext i1 %not.cmp to i32
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ret i32 %.
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}
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; Check 16 bytes - requires 2 loads for each param (or use vectors?).
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define signext i32 @zeroEqualityTest01(i8* %x, i8* %y) {
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; CHECK-LABEL: zeroEqualityTest01:
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; CHECK: # %bb.0:
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[ExpandMemCmp] Correctly set alignment of generated loads
Summary:
This is a part of the series of efforts for correcting alignment of memory operations.
(Another related bugs: https://bugs.llvm.org/show_bug.cgi?id=44388 , https://bugs.llvm.org/show_bug.cgi?id=44543 )
This fixes https://bugs.llvm.org/show_bug.cgi?id=43880 by giving default alignment of loads to 1.
The test CodeGen/AArch64/bcmp-inline-small.ll should have been changed; it was introduced by https://reviews.llvm.org/D64805 . I talked with @evandro, and confirmed that the test is okay to be changed.
Other two tests from PowerPC needed changes as well, but fixes were straightforward.
Reviewers: courbet
Reviewed By: courbet
Subscribers: nlopes, gchatelet, wuzish, nemanjai, kristof.beyls, hiraditya, steven.zhang, danielkiss, llvm-commits, evandro
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76113
2020-03-16 14:38:29 +01:00
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; CHECK-NEXT: ldx 5, 0, 3
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; CHECK-NEXT: ldx 6, 0, 4
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: cmpld 5, 6
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; CHECK-NEXT: bne 0, .LBB1_2
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; CHECK-NEXT: # %bb.1: # %loadbb1
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; CHECK-NEXT: ld 3, 8(3)
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; CHECK-NEXT: ld 4, 8(4)
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; CHECK-NEXT: cmpld 3, 4
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2020-08-17 20:42:57 +02:00
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; CHECK-NEXT: li 3, 0
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: beq 0, .LBB1_3
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; CHECK-NEXT: .LBB1_2: # %res_block
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; CHECK-NEXT: li 3, 1
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2020-08-17 20:42:57 +02:00
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; CHECK-NEXT: .LBB1_3: # %endblock
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; CHECK-NEXT: clrldi 3, 3, 32
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 16)
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%not.tobool = icmp ne i32 %call, 0
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%. = zext i1 %not.tobool to i32
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ret i32 %.
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}
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; Check 7 bytes - requires 3 loads for each param.
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define signext i32 @zeroEqualityTest03(i8* %x, i8* %y) {
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; CHECK-LABEL: zeroEqualityTest03:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lwz 5, 0(3)
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; CHECK-NEXT: lwz 6, 0(4)
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; CHECK-NEXT: cmplw 5, 6
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; CHECK-NEXT: bne 0, .LBB2_3
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; CHECK-NEXT: # %bb.1: # %loadbb1
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; CHECK-NEXT: lhz 5, 4(3)
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; CHECK-NEXT: lhz 6, 4(4)
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; CHECK-NEXT: cmplw 5, 6
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; CHECK-NEXT: bne 0, .LBB2_3
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; CHECK-NEXT: # %bb.2: # %loadbb2
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; CHECK-NEXT: lbz 3, 6(3)
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; CHECK-NEXT: lbz 4, 6(4)
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; CHECK-NEXT: cmplw 3, 4
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2020-08-17 20:42:57 +02:00
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; CHECK-NEXT: li 3, 0
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: beq 0, .LBB2_4
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; CHECK-NEXT: .LBB2_3: # %res_block
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; CHECK-NEXT: li 3, 1
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2020-08-17 20:42:57 +02:00
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; CHECK-NEXT: .LBB2_4: # %endblock
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; CHECK-NEXT: clrldi 3, 3, 32
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* %x, i8* %y, i64 7)
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%not.lnot = icmp ne i32 %call, 0
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%cond = zext i1 %not.lnot to i32
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ret i32 %cond
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}
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; Validate with > 0
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define signext i32 @zeroEqualityTest04() {
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; CHECK-LABEL: zeroEqualityTest04:
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2020-03-03 13:17:21 +01:00
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; CHECK: # %bb.0: # %loadbb
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2020-03-03 13:17:21 +01:00
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; CHECK-NEXT: li 3, 0
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest02.buffer2 to i8*), i64 16)
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%not.cmp = icmp slt i32 %call, 1
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%. = zext i1 %not.cmp to i32
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ret i32 %.
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}
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; Validate with < 0
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define signext i32 @zeroEqualityTest05() {
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; CHECK-LABEL: zeroEqualityTest05:
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2020-03-03 13:17:21 +01:00
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; CHECK: # %bb.0: # %loadbb
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2020-03-03 13:17:21 +01:00
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; CHECK-NEXT: li 3, 0
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer1 to i8*), i8* bitcast ([4 x i32]* @zeroEqualityTest03.buffer2 to i8*), i64 16)
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%call.lobit = lshr i32 %call, 31
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%call.lobit.not = xor i32 %call.lobit, 1
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ret i32 %call.lobit.not
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}
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; Validate with memcmp()?:
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define signext i32 @equalityFoldTwoConstants() {
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; CHECK-LABEL: equalityFoldTwoConstants:
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; CHECK: # %bb.0: # %loadbb
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16)
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%not.tobool = icmp eq i32 %call, 0
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%cond = zext i1 %not.tobool to i32
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ret i32 %cond
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}
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define signext i32 @equalityFoldOneConstant(i8* %X) {
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; CHECK-LABEL: equalityFoldOneConstant:
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; CHECK: # %bb.0:
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[ExpandMemCmp] Correctly set alignment of generated loads
Summary:
This is a part of the series of efforts for correcting alignment of memory operations.
(Another related bugs: https://bugs.llvm.org/show_bug.cgi?id=44388 , https://bugs.llvm.org/show_bug.cgi?id=44543 )
This fixes https://bugs.llvm.org/show_bug.cgi?id=43880 by giving default alignment of loads to 1.
The test CodeGen/AArch64/bcmp-inline-small.ll should have been changed; it was introduced by https://reviews.llvm.org/D64805 . I talked with @evandro, and confirmed that the test is okay to be changed.
Other two tests from PowerPC needed changes as well, but fixes were straightforward.
Reviewers: courbet
Reviewed By: courbet
Subscribers: nlopes, gchatelet, wuzish, nemanjai, kristof.beyls, hiraditya, steven.zhang, danielkiss, llvm-commits, evandro
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76113
2020-03-16 14:38:29 +01:00
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; CHECK-NEXT: ldx 4, 0, 3
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: cmpld 4, 5
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; CHECK-NEXT: bne 0, .LBB6_2
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; CHECK-NEXT: # %bb.1: # %loadbb1
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; CHECK-NEXT: li 4, 3
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; CHECK-NEXT: ld 3, 8(3)
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: ori 4, 4, 2
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; CHECK-NEXT: cmpld 3, 4
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2020-08-17 20:42:57 +02:00
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: beq 0, .LBB6_3
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2019-09-10 12:39:09 +02:00
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; CHECK-NEXT: .LBB6_2: # %res_block
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: .LBB6_3: # %endblock
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: srwi 3, 3, 5
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; CHECK-NEXT: blr
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%call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* %X, i64 16)
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%not.tobool = icmp eq i32 %call, 0
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%cond = zext i1 %not.tobool to i32
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ret i32 %cond
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}
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define i1 @length2_eq_nobuiltin_attr(i8* %X, i8* %Y) nounwind {
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; CHECK-LABEL: length2_eq_nobuiltin_attr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: std 0, 16(1)
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; CHECK-NEXT: stdu 1, -32(1)
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; CHECK-NEXT: li 5, 2
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; CHECK-NEXT: bl memcmp
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; CHECK-NEXT: nop
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; CHECK-NEXT: cntlzw 3, 3
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; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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%m = tail call signext i32 @memcmp(i8* %X, i8* %Y, i64 2) nobuiltin
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%c = icmp eq i32 %m, 0
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ret i1 %c
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}
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