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llvm-mirror/test/MC/X86/intel-syntax.s

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Add new test. llvm-svn: 148128
2012-01-13 19:45:31 +01:00
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s
Intel syntax: Ignore mnemonic aliases. llvm-svn: 148316
2012-01-17 19:30:45 +01:00
_test:
xor EAX, EAX
ret
_main:
Add new test. llvm-svn: 148128
2012-01-13 19:45:31 +01:00
// CHECK: movl $257, -4(%rsp)
mov DWORD PTR [RSP - 4], 257
Intel syntax: Do not unncessarily create plus expression for memory operand displacement. llvm-svn: 148321
2012-01-17 20:08:07 +01:00
// CHECK: movl $258, 4(%rsp)
mov DWORD PTR [RSP + 4], 258
Add new test. llvm-svn: 148128
2012-01-13 19:45:31 +01:00
// CHECK: movq $123, -16(%rsp)
mov QWORD PTR [RSP - 16], 123
// CHECK: movb $97, -17(%rsp)
mov BYTE PTR [RSP - 17], 97
// CHECK: movl -4(%rsp), %eax
mov EAX, DWORD PTR [RSP - 4]
Intel syntax: Robustify memory operand parsing. llvm-svn: 148312
2012-01-17 19:00:18 +01:00
// CHECK: movq (%rsp), %rax
mov RAX, QWORD PTR [RSP]
// CHECK: movl $-4, -4(%rsp)
mov DWORD PTR [RSP - 4], -4
// CHECK: movq 0, %rcx
mov RCX, QWORD PTR [0]
// CHECK: movl -24(%rsp,%rax,4), %eax
mov EAX, DWORD PTR [RSP + 4*RAX - 24]
Intel syntax: Parse "BYTE PTR [RDX + RCX]" llvm-svn: 148334
2012-01-17 22:25:10 +01:00
// CHECK: movb %dil, (%rdx,%rcx)
mov BYTE PTR [RDX + RCX], DIL
Intel syntax: Fix parser match class to check memory operand size. llvm-svn: 148338
2012-01-17 22:48:03 +01:00
// CHECK: movzwl 2(%rcx), %edi
movzx EDI, WORD PTR [RCX + 2]
Intel syntax: Ignore mnemonic aliases. llvm-svn: 148316
2012-01-17 19:30:45 +01:00
// CHECK: callq _test
call _test
Process instructions after match to select alternative encoding which may be more desirable. llvm-svn: 148431
2012-01-18 23:42:29 +01:00
// CHECK: andw $12, %ax
and ax, 12
// CHECK: andw $-12, %ax
and ax, -12
// CHECK: andw $257, %ax
and ax, 257
// CHECK: andw $-257, %ax
and ax, -257
// CHECK: andl $12, %eax
and eax, 12
// CHECK: andl $-12, %eax
and eax, -12
// CHECK: andl $257, %eax
and eax, 257
// CHECK: andl $-257, %eax
and eax, -257
// CHECK: andq $12, %rax
and rax, 12
// CHECK: andq $-12, %rax
and rax, -12
// CHECK: andq $257, %rax
and rax, 257
// CHECK: andq $-257, %rax
and rax, -257
Intel syntax: Robustify register parsing. llvm-svn: 148591
2012-01-20 23:32:05 +01:00
// CHECK: fld %st(0)
fld ST(0)
Intel syntax: Parse segment registers. llvm-svn: 148712
2012-01-23 19:31:58 +01:00
// CHECK: movl %fs:(%rdi), %eax
[ms-inline asm] Extend support for parsing Intel bracketed memory operands that have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 llvm-svn: 172484
2013-01-14 23:31:35 +01:00
mov EAX, DWORD PTR FS:[RDI]
// CHECK: leal (,%rdi,4), %r8d
lea R8D, DWORD PTR [4*RDI]
// CHECK: movl _fnan(,%ecx,4), %ecx
mov ECX, DWORD PTR [4*ECX + _fnan]
// CHECK: movq %fs:320, %rax
mov RAX, QWORD PTR FS:[320]
[ms-inline asm] Support offsets after segment registers Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 llvm-svn: 189407
2013-08-27 23:56:17 +02:00
// CHECK: movq %fs:320, %rax
mov RAX, QWORD PTR FS:320
// CHECK: movq %rax, %fs:320
mov QWORD PTR FS:320, RAX
// CHECK: movq %rax, %fs:20(%rbx)
mov QWORD PTR FS:20[rbx], RAX
Fixing Intel format of the vshufpd instruction. Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
2013-09-27 03:44:23 +02:00
// CHECK: vshufpd $1, %xmm2, %xmm1, %xmm0
vshufpd XMM0, XMM1, XMM2, 1
[ms-inline asm] Extend support for parsing Intel bracketed memory operands that have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 llvm-svn: 172484
2013-01-14 23:31:35 +01:00
// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
// CHECK: movsd -8, %xmm5
movsd XMM5, QWORD PTR [-8]
// CHECK: movl %ecx, (%eax)
mov [eax], ecx
// CHECK: movl %ecx, (,%ebx,4)
mov [4*ebx], ecx
// CHECK: movl %ecx, (,%ebx,4)
mov [ebx*4], ecx
// CHECK: movl %ecx, 1024
mov [1024], ecx
// CHECK: movl %ecx, 4132
mov [0x1024], ecx
// CHECK: movl %ecx, 32
mov [16 + 16], ecx
// CHECK: movl %ecx, 0
mov [16 - 16], ecx
// CHECK: movl %ecx, 32
mov [16][16], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax + 4*ebx], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax + ebx*4], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [4*ebx + eax], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [ebx*4 + eax], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax][4*ebx], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax][ebx*4], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [4*ebx][eax], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [ebx*4][eax], ecx
// CHECK: movl %ecx, 12(%eax)
mov [eax + 12], ecx
// CHECK: movl %ecx, 12(%eax)
mov [12 + eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax + 16 + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + eax + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + 16 + eax], ecx
// CHECK: movl %ecx, 12(%eax)
mov [eax][12], ecx
// CHECK: movl %ecx, 12(%eax)
mov [12][eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax][16 + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax + 16][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax][16][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][eax + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + eax][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][16 + eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + 16][eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax][16][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][eax][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][16][eax], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [4*ebx + 16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [ebx*4 + 16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [4*ebx][16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [ebx*4][16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16 + 4*ebx], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16 + ebx*4], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16][4*ebx], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 4*ebx + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16 + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + 16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][4*ebx + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16 + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 4*ebx][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + 16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][4*ebx][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + ebx*4 + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16 + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + 16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][ebx*4 + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16 + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + ebx*4][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + 16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][ebx*4][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][ebx*4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 16], ecx
[ms-inline asm] Add support for numeric displacement expressions in bracketed memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 llvm-svn: 178881
2013-04-05 18:28:55 +02:00
// CHECK: prefetchnta 12800(%esi)
prefetchnta [esi + (200*64)]
// CHECK: prefetchnta 32(%esi)
prefetchnta [esi + (64/2)]
// CHECK: prefetchnta 128(%esi)
prefetchnta [esi + (64/2*4)]
// CHECK: prefetchnta 8(%esi)
prefetchnta [esi + (64/(2*4))]
// CHECK: prefetchnta 48(%esi)
prefetchnta [esi + (64/(2*4)+40)]
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 2*8], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][4*ebx - 2*8], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + 4*ebx - 2*8], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [12 + eax + (4*ebx) - 2*14], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 2*2*2*2], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - (2*8)], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 2 * 8 + 4 - 4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + ebx*4 - 2 * 8 + 4 - 4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + ebx*4 - 2 * ((8 + 4) - 4)], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [-2 * ((8 + 4) - 4) + eax + ebx*4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [((-2) * ((8 + 4) - 4)) + eax + ebx*4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + ((-2) * ((8 + 4) - 4)) + ebx*4], ecx
[ms-inline asm] Add support for the minus unary operator. Previously, we were unable to handle cases such as __asm mov eax, 8*-8. This patch also attempts to simplify the state machine. Further, the error reporting has been improved. Test cases included, but more will be added to the clang side shortly. rdar://13668445 llvm-svn: 179719
2013-04-17 23:01:45 +02:00
// CHECK: movl %ecx, 96(%eax,%ebx,4)
mov [eax + ((-2) * ((8 + 4) * -4)) + ebx*4], ecx
// CHECK: movl %ecx, -8(%eax,%ebx,4)
mov [eax][-8][ebx*4], ecx
// CHECK: movl %ecx, -2(%eax,%ebx,4)
mov [eax][16/-8][ebx*4], ecx
// CHECK: movl %ecx, -2(%eax,%ebx,4)
mov [eax][(16)/-8][ebx*4], ecx
[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. llvm-svn: 179813
2013-04-19 01:16:12 +02:00
// CHECK: setb %al
setc al
// CHECK: sete %al
setz al
// CHECK: setbe %al
setna al
// CHECK: setae %al
setnb al
// CHECK: setae %al
setnc al
// CHECK: setle %al
setng al
// CHECK: setge %al
setnl al
// CHECK: setne %al
setnz al
// CHECK: setp %al
setpe al
// CHECK: setnp %al
setpo al
// CHECK: setb %al
setnae al
// CHECK: seta %al
setnbe al
// CHECK: setl %al
setnge al
// CHECK: setg %al
setnle al
Add test case for PR15779, which has previously been fixed. llvm-svn: 180058
2013-04-23 00:30:01 +02:00
// CHECK: jne _foo
jnz _foo
[x86AsmParser] It's valid to stop parsing an operand at an immediate. rdar://13854369 and PR15944 llvm-svn: 181564
2013-05-10 01:48:53 +02:00
// CHECK: outb %al, $4
out 4, al
[ms-inline asm] Add support for numeric displacement expressions in bracketed memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 llvm-svn: 178881
2013-04-05 18:28:55 +02:00
ret
X86: Make the cmov aliases work with intel syntax too. llvm-svn: 183907
2013-06-13 17:45:24 +02:00
// CHECK: cmovbl %ebx, %eax
cmovc eax, ebx
// CHECK: cmovel %ebx, %eax
cmovz eax, ebx
// CHECK: cmovbel %ebx, %eax
cmovna eax, ebx
// CHECK: cmovael %ebx, %eax
cmovnb eax, ebx
// CHECK: cmovael %ebx, %eax
cmovnc eax, ebx
// CHECK: cmovlel %ebx, %eax
cmovng eax, ebx
// CHECK: cmovgel %ebx, %eax
cmovnl eax, ebx
// CHECK: cmovnel %ebx, %eax
cmovnz eax, ebx
// CHECK: cmovpl %ebx, %eax
cmovpe eax, ebx
// CHECK: cmovnpl %ebx, %eax
cmovpo eax, ebx
// CHECK: cmovbl %ebx, %eax
cmovnae eax, ebx
// CHECK: cmoval %ebx, %eax
cmovnbe eax, ebx
// CHECK: cmovll %ebx, %eax
cmovnge eax, ebx
// CHECK: cmovgl %ebx, %eax
cmovnle eax, ebx
Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately. llvm-svn: 187188
2013-07-26 07:39:33 +02:00
// CHECK: shldw %cl, %bx, %dx
// CHECK: shldw %cl, %bx, %dx
// CHECK: shldw $1, %bx, %dx
// CHECK: shldw %cl, %bx, (%rax)
// CHECK: shldw %cl, %bx, (%rax)
// CHECK: shrdw %cl, %bx, %dx
// CHECK: shrdw %cl, %bx, %dx
// CHECK: shrdw $1, %bx, %dx
// CHECK: shrdw %cl, %bx, (%rax)
// CHECK: shrdw %cl, %bx, (%rax)
shld DX, BX
shld DX, BX, CL
shld DX, BX, 1
shld [RAX], BX
shld [RAX], BX, CL
shrd DX, BX
shrd DX, BX, CL
shrd DX, BX, 1
shrd [RAX], BX
shrd [RAX], BX, CL
// CHECK: btl $1, (%eax)
// CHECK: btsl $1, (%eax)
// CHECK: btrl $1, (%eax)
// CHECK: btcl $1, (%eax)
bt DWORD PTR [EAX], 1
bt DWORD PTR [EAX], 1
bts DWORD PTR [EAX], 1
btr DWORD PTR [EAX], 1
btc DWORD PTR [EAX], 1
//CHECK: divb %bl
//CHECK: divw %bx
//CHECK: divl %ecx
//CHECK: divl 3735928559(%ebx,%ecx,8)
//CHECK: divl 69
//CHECK: divl 32493
//CHECK: divl 3133065982
//CHECK: divl 305419896
//CHECK: idivb %bl
//CHECK: idivw %bx
//CHECK: idivl %ecx
//CHECK: idivl 3735928559(%ebx,%ecx,8)
//CHECK: idivl 69
//CHECK: idivl 32493
//CHECK: idivl 3133065982
//CHECK: idivl 305419896
div AL, BL
div AX, BX
div EAX, ECX
div EAX, [ECX*8+EBX+0xdeadbeef]
div EAX, [0x45]
div EAX, [0x7eed]
div EAX, [0xbabecafe]
div EAX, [0x12345678]
idiv AL, BL
idiv AX, BX
idiv EAX, ECX
idiv EAX, [ECX*8+EBX+0xdeadbeef]
idiv EAX, [0x45]
idiv EAX, [0x7eed]
idiv EAX, [0xbabecafe]
idiv EAX, [0x12345678]
// CHECK: inb %dx, %al
// CHECK: inw %dx, %ax
// CHECK: inl %dx, %eax
// CHECK: outb %al, %dx
// CHECK: outw %ax, %dx
// CHECK: outl %eax, %dx
inb DX
inw DX
inl DX
outb DX
outw DX
outl DX
// CHECK: xchgq %rcx, %rax
// CHECK: xchgq %rcx, %rax
// CHECK: xchgl %ecx, %eax
// CHECK: xchgl %ecx, %eax
// CHECK: xchgw %cx, %ax
// CHECK: xchgw %cx, %ax
xchg RAX, RCX
xchg RCX, RAX
xchg EAX, ECX
xchg ECX, EAX
xchg AX, CX
xchg CX, AX
// CHECK: xchgq %rax, (%ecx)
// CHECK: xchgq %rax, (%ecx)
// CHECK: xchgl %eax, (%ecx)
// CHECK: xchgl %eax, (%ecx)
// CHECK: xchgw %ax, (%ecx)
// CHECK: xchgw %ax, (%ecx)
xchg RAX, [ECX]
xchg [ECX], RAX
xchg EAX, [ECX]
xchg [ECX], EAX
xchg AX, [ECX]
xchg [ECX], AX
// CHECK: testq (%ecx), %rax
// CHECK: testq (%ecx), %rax
// CHECK: testl (%ecx), %eax
// CHECK: testl (%ecx), %eax
// CHECK: testw (%ecx), %ax
// CHECK: testw (%ecx), %ax
// CHECK: testb (%ecx), %al
// CHECK: testb (%ecx), %al
test RAX, [ECX]
test [ECX], RAX
test EAX, [ECX]
test [ECX], EAX
test AX, [ECX]
test [ECX], AX
test AL, [ECX]
test [ECX], AL
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
// CHECK: fnstsw %ax
fnstsw
fnstsw AX
fnstsw EAX
fnstsw AL
// CHECK: faddp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fsubp %st(1)
// CHECK: fdivrp %st(1)
// CHECK: fdivp %st(1)
faddp ST(1), ST(0)
fmulp ST(1), ST(0)
fsubp ST(1), ST(0)
fsubrp ST(1), ST(0)
fdivp ST(1), ST(0)
fdivrp ST(1), ST(0)
// CHECK: faddp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fsubp %st(1)
// CHECK: fdivrp %st(1)
// CHECK: fdivp %st(1)
faddp ST(0), ST(1)
fmulp ST(0), ST(1)
fsubp ST(0), ST(1)
fsubrp ST(0), ST(1)
fdivp ST(0), ST(1)
fdivrp ST(0), ST(1)
// CHECK: faddp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fsubp %st(1)
// CHECK: fdivrp %st(1)
// CHECK: fdivp %st(1)
faddp ST(1)
fmulp ST(1)
fsubp ST(1)
fsubrp ST(1)
fdivp ST(1)
fdivrp ST(1)
[x86] translating "fp" (floating point) instructions from {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp} LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr. GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions. Differential Revision: http://reviews.llvm.org/D14217 llvm-svn: 252908
2015-11-12 17:58:51 +01:00
// CHECK: faddp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fsubp %st(1)
// CHECK: fdivrp %st(1)
// CHECK: fdivp %st(1)
fadd
fmul
fsub
fsubr
fdiv
fdivr
Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately. llvm-svn: 187188
2013-07-26 07:39:33 +02:00
// CHECK: faddp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fsubp %st(1)
// CHECK: fdivrp %st(1)
// CHECK: fdivp %st(1)
faddp
fmulp
fsubp
fsubrp
fdivp
fdivrp
// CHECK: fadd %st(1)
// CHECK: fmul %st(1)
// CHECK: fsub %st(1)
// CHECK: fsubr %st(1)
// CHECK: fdiv %st(1)
// CHECK: fdivr %st(1)
fadd ST(0), ST(1)
fmul ST(0), ST(1)
fsub ST(0), ST(1)
fsubr ST(0), ST(1)
fdiv ST(0), ST(1)
fdivr ST(0), ST(1)
// CHECK: fadd %st(0), %st(1)
// CHECK: fmul %st(0), %st(1)
// CHECK: fsubr %st(0), %st(1)
// CHECK: fsub %st(0), %st(1)
// CHECK: fdivr %st(0), %st(1)
// CHECK: fdiv %st(0), %st(1)
fadd ST(1), ST(0)
fmul ST(1), ST(0)
fsub ST(1), ST(0)
fsubr ST(1), ST(0)
fdiv ST(1), ST(0)
fdivr ST(1), ST(0)
// CHECK: fadd %st(1)
// CHECK: fmul %st(1)
// CHECK: fsub %st(1)
// CHECK: fsubr %st(1)
// CHECK: fdiv %st(1)
// CHECK: fdivr %st(1)
fadd ST(1)
fmul ST(1)
fsub ST(1)
fsubr ST(1)
fdiv ST(1)
fdivr ST(1)
Fix intel syntax for 64-bit version of FXSAVE/FXRSTOR to use '64' suffix instead of 'q' llvm-svn: 199474
2014-01-17 08:25:39 +01:00
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 12:03:57 +01:00
// CHECK: fxsave64 (%rax)
// CHECK: fxrstor64 (%rax)
Teach x86 asm parser to handle 'opaque ptr' in Intel syntax. llvm-svn: 199477
2014-01-17 08:44:10 +01:00
fxsave64 opaque ptr [rax]
fxrstor64 opaque ptr [rax]
MC: Fix Intel assembly parser for [global + offset] We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. llvm-svn: 202774
2014-03-04 01:33:17 +01:00
.bss
.globl _g0
.text
// CHECK: movq _g0, %rbx
// CHECK: movq _g0+8, %rcx
mov rbx, qword ptr [_g0]
mov rcx, qword ptr [_g0 + 8]
MS asm: Properly handle quoted symbol names We would get confused by '@' characters in symbol names, we would mistake the text following them for the variant kind. When an identifier a string, the variant kind will never show up inside of it. Instead, check to see if there is a variant following the string. This fixes PR19965. llvm-svn: 211249
2014-06-19 03:25:43 +02:00
"?half@?0??bar@@YAXXZ@4NA":
.quad 4602678819172646912
X86 MC: Handle instructions like fxsave that match multiple operand sizes Instructions like 'fxsave' and control flow instructions like 'jne' match any operand size. The loop I added to the Intel syntax matcher assumed that using a different size would give a different instruction. Now it handles the case where we get the same instruction for different memory operand sizes. This also allows us to remove the hack we had for unsized absolute memory operands, because we can successfully match things like 'jnz' without reporting ambiguity. Removing this hack uncovered test case involving 'fadd' that was ambiguous. The memory operand could have been single or double precision. llvm-svn: 216604
2014-08-27 22:10:38 +02:00
fadd dword ptr "?half@?0??bar@@YAXXZ@4NA"
fadd dword ptr "?half@?0??bar@@YAXXZ@4NA"@IMGREL
MS asm: Properly handle quoted symbol names We would get confused by '@' characters in symbol names, we would mistake the text following them for the variant kind. When an identifier a string, the variant kind will never show up inside of it. Instead, check to see if there is a variant following the string. This fixes PR19965. llvm-svn: 211249
2014-06-19 03:25:43 +02:00
// CHECK: fadds "?half@?0??bar@@YAXXZ@4NA"
MC: Use @IMGREL instead of @IMGREL32, which we can't parse Nico Rieck added support for this 32-bit COFF relocation some time ago for Win64 stuff. It appears that as an oversight, the assembly output used "foo"@IMGREL32 instead of "foo"@IMGREL, which is what we can parse. Sadly, there were actually tests that took in IMGREL and put out IMGREL32, and we didn't notice the inconsistency. Oh well. Now LLVM can assemble it's own output with slightly more fidelity. llvm-svn: 218437
2014-09-25 04:09:18 +02:00
// CHECK: fadds "?half@?0??bar@@YAXXZ@4NA"@IMGREL
MC: Split the x86 asm matcher implementations by dialect The existing matcher has lots of AT&T assembly dialect assumptions baked into it. In particular, the hack for resolving the size of a memory operand by appending the four most common suffixes doesn't work at all. The Intel assembly dialect mnemonic table has ambiguous entries, so we need to try matching multiple times with different operand sizes, since that's the only way to choose different instruction variants. This makes us more compatible with gas's implementation of Intel assembly syntax. MSVC assumes you want byte-sized operations for the instructions that we reject as ambiguous. Reviewed By: grosbach Differential Revision: http://reviews.llvm.org/D4747 llvm-svn: 216481
2014-08-26 22:32:34 +02:00
inc qword ptr [rax]
inc dword ptr [rax]
inc word ptr [rax]
inc byte ptr [rax]
// CHECK: incq (%rax)
// CHECK: incl (%rax)
// CHECK: incw (%rax)
// CHECK: incb (%rax)
dec qword ptr [rax]
dec dword ptr [rax]
dec word ptr [rax]
dec byte ptr [rax]
// CHECK: decq (%rax)
// CHECK: decl (%rax)
// CHECK: decw (%rax)
// CHECK: decb (%rax)
add qword ptr [rax], 1
add dword ptr [rax], 1
add word ptr [rax], 1
add byte ptr [rax], 1
// CHECK: addq $1, (%rax)
// CHECK: addl $1, (%rax)
// CHECK: addw $1, (%rax)
// CHECK: addb $1, (%rax)
[X86] Add support for tbyte memory operand size for Intel-syntax x86 assembly Differential Revision: http://reviews.llvm.org/D11257 Patch by: marina.yatsina@intel.com llvm-svn: 242639
2015-07-19 13:03:08 +02:00
fstp tbyte ptr [rax]
MC: Split the x86 asm matcher implementations by dialect The existing matcher has lots of AT&T assembly dialect assumptions baked into it. In particular, the hack for resolving the size of a memory operand by appending the four most common suffixes doesn't work at all. The Intel assembly dialect mnemonic table has ambiguous entries, so we need to try matching multiple times with different operand sizes, since that's the only way to choose different instruction variants. This makes us more compatible with gas's implementation of Intel assembly syntax. MSVC assumes you want byte-sized operations for the instructions that we reject as ambiguous. Reviewed By: grosbach Differential Revision: http://reviews.llvm.org/D4747 llvm-svn: 216481
2014-08-26 22:32:34 +02:00
fstp xword ptr [rax]
fstp qword ptr [rax]
fstp dword ptr [rax]
// CHECK: fstpt (%rax)
[X86] Add support for tbyte memory operand size for Intel-syntax x86 assembly Differential Revision: http://reviews.llvm.org/D11257 Patch by: marina.yatsina@intel.com llvm-svn: 242639
2015-07-19 13:03:08 +02:00
// CHECK: fstpt (%rax)
MC: Split the x86 asm matcher implementations by dialect The existing matcher has lots of AT&T assembly dialect assumptions baked into it. In particular, the hack for resolving the size of a memory operand by appending the four most common suffixes doesn't work at all. The Intel assembly dialect mnemonic table has ambiguous entries, so we need to try matching multiple times with different operand sizes, since that's the only way to choose different instruction variants. This makes us more compatible with gas's implementation of Intel assembly syntax. MSVC assumes you want byte-sized operations for the instructions that we reject as ambiguous. Reviewed By: grosbach Differential Revision: http://reviews.llvm.org/D4747 llvm-svn: 216481
2014-08-26 22:32:34 +02:00
// CHECK: fstpl (%rax)
// CHECK: fstps (%rax)
X86 MC: Handle instructions like fxsave that match multiple operand sizes Instructions like 'fxsave' and control flow instructions like 'jne' match any operand size. The loop I added to the Intel syntax matcher assumed that using a different size would give a different instruction. Now it handles the case where we get the same instruction for different memory operand sizes. This also allows us to remove the hack we had for unsized absolute memory operands, because we can successfully match things like 'jnz' without reporting ambiguity. Removing this hack uncovered test case involving 'fadd' that was ambiguous. The memory operand could have been single or double precision. llvm-svn: 216604
2014-08-27 22:10:38 +02:00
fxsave [eax]
fsave [eax]
fxrstor [eax]
frstor [eax]
// CHECK: fxsave (%eax)
// CHECK: wait
// CHECK: fnsave (%eax)
// CHECK: fxrstor (%eax)
// CHECK: frstor (%eax)
// FIXME: Should we accept this? Masm accepts it, but gas does not.
fxsave dword ptr [eax]
fsave dword ptr [eax]
fxrstor dword ptr [eax]
frstor dword ptr [eax]
// CHECK: fxsave (%eax)
// CHECK: wait
// CHECK: fnsave (%eax)
// CHECK: fxrstor (%eax)
// CHECK: frstor (%eax)
[TableGen][AsmMatcherEmitter] Only parse isolated tokens as registers. Fixes PR23455, where, when TableGen generates the matcher from the AsmString, it splits "cmp${cc}ss" into tokens, and the "ss" suffix is recognized as the SS register. I can't think of a situation where that's a feature, not a bug, hence: when a token is "isolated", i.e., it is followed and preceded by separators, it shouldn't be parsed as a register. Differential Revision: http://reviews.llvm.org/D9844 llvm-svn: 238536
2015-05-29 03:03:37 +02:00
// CHECK: cmpnless %xmm1, %xmm0
cmpnless xmm0, xmm1
[X86] Fix order of operands for ins and outs instructions when parsing intel syntax Patch by: marina.yatsina@intel.com Differential Revision: http://reviews.llvm.org/D11337 llvm-svn: 243001
2015-07-23 12:23:48 +02:00
insb
insw
insd
// CHECK: insb %dx, %es:(%rdi)
// CHECK: insw %dx, %es:(%rdi)
// CHECK: insl %dx, %es:(%rdi)
outsb
outsw
outsd
// CHECK: outsb (%rsi), %dx
// CHECK: outsw (%rsi), %dx
// CHECK: outsl (%rsi), %dx
[X86] Fix imul alias for intel syntax The "imul reg, imm" alias is not defined for intel syntax. In intel syntax there is no w/l/q suffix for the imul instruction. Differential Revision: http://reviews.llvm.org/D11887 llvm-svn: 244582
2015-08-11 12:43:04 +02:00
imul bx, 123
imul ebx, 123
imul rbx, 123
// CHECK: imulw $123, %bx
// CHECK: imull $123, %ebx
// CHECK: imulq $123, %rbx
[X86] Fix REPE, REPZ, REPNZ for intel syntax REPE, REPZ, REPNZ, REPNE should have mnemonics for Intel syntax as well. Currently using these instructions causes compilation errors for Intel syntax. Differential Revision: http://reviews.llvm.org/D11794 llvm-svn: 244584
2015-08-11 13:28:10 +02:00
repe cmpsb
repz cmpsb
repne cmpsb
repnz cmpsb
// CHECK: rep
// CHECK: cmpsb %es:(%rdi), (%rsi)
// CHECK: rep
// CHECK: cmpsb %es:(%rdi), (%rsi)
// CHECK: repne
// CHECK: cmpsb %es:(%rdi), (%rsi)
// CHECK: repne
// CHECK: cmpsb %es:(%rdi), (%rsi)
[X86] Add SAL mnemonics for Intel syntax SAL and SHL instructions perform the same operation Differential Revision: http://reviews.llvm.org/D11882 llvm-svn: 244588
2015-08-11 14:05:06 +02:00
sal eax, 123
// CHECK: shll $123, %eax
[X86] Fix bug in COMISD and COMISS definition in td files COMISD should receive QWORD because it is defined as (V)COMISD xmm1, xmm2/m64 COMISS should receive DWORD because it is defined as (V)COMISS xmm1, xmm2/m32 Differential Revision: http://reviews.llvm.org/D11712 llvm-svn: 245551
2015-08-20 13:21:36 +02:00
[X86] Add support for mmword memory operand size for Intel-syntax x86 assembly Differential Revision: http://reviews.llvm.org/D12151 llvm-svn: 245835
2015-08-24 12:26:54 +02:00
psignw mm0, MMWORD PTR t2
// CHECK: psignw t2, %mm0
[X86] Fix bug in COMISD and COMISS definition in td files COMISD should receive QWORD because it is defined as (V)COMISD xmm1, xmm2/m64 COMISS should receive DWORD because it is defined as (V)COMISS xmm1, xmm2/m32 Differential Revision: http://reviews.llvm.org/D11712 llvm-svn: 245551
2015-08-20 13:21:36 +02:00
comisd xmm0, QWORD PTR [eax]
comiss xmm0, DWORD PTR [eax]
vcomisd xmm0, QWORD PTR [eax]
vcomiss xmm0, DWORD PTR [eax]
// CHECK: comisd (%eax), %xmm0
// CHECK: comiss (%eax), %xmm0
// CHECK: vcomisd (%eax), %xmm0
// CHECK: vcomiss (%eax), %xmm0
[X86] Fix FBLD and FBSTP FBLD and FBSTP should receive TBYTE because it is defined as FBLD m80 FBSTP m80 Differential Revision: http://reviews.llvm.org/D11748 llvm-svn: 245553
2015-08-20 13:51:24 +02:00
fbld tbyte ptr [eax]
fbstp tbyte ptr [eax]
// CHECK: fbld (%eax)
// CHECK: fbstp (%eax)
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