Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
//=- AArch64RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// General Purpose Registers: W, X.
|
|
|
|
def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
|
|
|
|
|
|
|
|
/// Floating Point/Vector Registers: B, H, S, D, Q.
|
|
|
|
def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
|
|
|
|
|
|
|
|
/// Conditional register: NZCV.
|
2017-10-18 02:12:43 +02:00
|
|
|
def CCRegBank : RegisterBank<"CC", [CCR]>;
|