llvm-mirror/test/MC/ARM/thumb.s

@ RUN: llvm-mc -triple thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
        .code 16

        cmp     r1, r2
@ CHECK: cmp	r1, r2                  @ encoding: [0x91,0x42]

        pop     {r1, r2, r4}
@ CHECK: pop    {r1, r2, r4}            @ encoding: [0x16,0xbc]

        trap
@ CHECK: trap                           @ encoding: [0xfe,0xde]

	blx	r9
        blx r10
@ CHECK: blx	r9                      @ encoding: [0xc8,0x47]
@ CHECK: blx	r10                     @ encoding: [0xd0,0x47]

        rev     r2, r3
        rev16   r3, r4
        revsh   r5, r6
@ CHECK: rev	r2, r3                  @ encoding: [0x1a,0xba]
@ CHECK: rev16	r3, r4                  @ encoding: [0x63,0xba]
@ CHECK: revsh	r5, r6                  @ encoding: [0xf5,0xba]

	sxtb	r2, r3
	sxth	r2, r3
@ CHECK: sxtb	r2, r3                  @ encoding: [0x5a,0xb2]
@ CHECK: sxth	r2, r3                  @ encoding: [0x1a,0xb2]

	tst	r4, r5
@ CHECK: tst	r4, r5                  @ encoding: [0x2c,0x42]

	uxtb	r3, r6
	uxth	r3, r6
@ CHECK: uxtb	r3, r6                  @ encoding: [0xf3,0xb2]
@ CHECK: uxth	r3, r6                  @ encoding: [0xb3,0xb2]

	ldr	r3, [r1, r2]
@ CHECK: ldr	r3, [r1, r2]            @ encoding: [0x8b,0x58]

        bkpt  #2
@ CHECK: bkpt  #2                       @ encoding: [0x02,0xbe]

        nop
@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46]

        cpsie aif
@ CHECK: cpsie aif                      @ encoding: [0x67,0xb6]

        mov  r0, pc
@ CHECK: mov  r0, pc                    @ encoding: [0x78,0x46]
Add Thumb encodings for REV instructions. llvm-svn: 120277 2010-11-29 01:42:50 +01:00			`@ RUN: llvm-mc -triple thumbv6-apple-darwin -show-encoding < %s \| FileCheck %s`
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx lr" instruction cannot be tested just yet. It requires matching a "condition code", but adding one of those makes things go south quickly... llvm-svn: 119774 2010-11-19 02:33:10 +01:00			`.code 16`

			`cmp r1, r2`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: cmp r1, r2 @ encoding: [0x91,0x42]`
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx lr" instruction cannot be tested just yet. It requires matching a "condition code", but adding one of those makes things go south quickly... llvm-svn: 119774 2010-11-19 02:33:10 +01:00
			`pop {r1, r2, r4}`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc]`
Add encoding for ARM "trap" instruction. llvm-svn: 119938 2010-11-21 12:05:29 +01:00
			`trap`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: trap @ encoding: [0xfe,0xde]`
Add more Thumb encodings. llvm-svn: 120272 2010-11-29 01:18:15 +01:00
			`blx r9`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`blx r10`
			`@ CHECK: blx r9 @ encoding: [0xc8,0x47]`
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan. llvm-svn: 131189 2011-05-11 19:00:48 +02:00			`@ CHECK: blx r10 @ encoding: [0xd0,0x47]`
Add Thumb encodings for REV instructions. llvm-svn: 120277 2010-11-29 01:42:50 +01:00
			`rev r2, r3`
			`rev16 r3, r4`
			`revsh r5, r6`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: rev r2, r3 @ encoding: [0x1a,0xba]`
			`@ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba]`
			`@ CHECK: revsh r5, r6 @ encoding: [0xf5,0xba]`
More Thumb encodings. llvm-svn: 120278 2010-11-29 02:00:43 +01:00
			`sxtb r2, r3`
			`sxth r2, r3`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2]`
			`@ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2]`
Add more Thumb encodings. llvm-svn: 120279 2010-11-29 02:07:48 +01:00
			`tst r4, r5`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: tst r4, r5 @ encoding: [0x2c,0x42]`
Add more Thumb encodings. llvm-svn: 120279 2010-11-29 02:07:48 +01:00
			`uxtb r3, r6`
			`uxth r3, r6`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2]`
			`@ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2]`
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. llvm-svn: 120408 2010-11-30 08:44:32 +01:00
			`ldr r3, [r1, r2]`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: ldr r3, [r1, r2] @ encoding: [0x8b,0x58]`
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. llvm-svn: 123772 2011-01-18 21:55:11 +01:00
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`bkpt #2`
			`@ CHECK: bkpt #2 @ encoding: [0x02,0xbe]`
Add mcr* and mr*c support to thumb targets llvm-svn: 123917 2011-01-20 17:35:57 +01:00
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions llvm-svn: 124288 2011-01-26 14:28:14 +01:00			`nop`
ARM: fix thumb1 nop decoding In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8. However the disassembler should not use this alias. llvm-svn: 184703 2013-06-24 11:11:53 +02:00			`@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46]`
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions llvm-svn: 124288 2011-01-26 14:28:14 +01:00
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489 2011-02-14 14:09:44 +01:00			`cpsie aif`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: cpsie aif @ encoding: [0x67,0xb6]`
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. llvm-svn: 132233 2011-05-28 01:46:09 +02:00
			`mov r0, pc`
Tidy up formatting. llvm-svn: 137464 2011-08-12 19:01:02 +02:00			`@ CHECK: mov r0, pc @ encoding: [0x78,0x46]`