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llvm-mirror/test/MC/AArch64/armv8.5a-bti.s

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[AArch64] Allow BTI mnemonics in the HINT space with BTI disabled Summary: It is important to emit HINT instructions instead of BTI ones when BTI is disabled. This allows compatibility with other assemblers (e.g. GAS). Still, developers of assembly code will want to write code that is compatible with both pre- and post-BTI CPUs. They could use HINT mnemonics, but the new mnemonics are a lot more readable (e.g. bti c instead of hint #34), and they will result in the same encodings. So, while LLVM should not *emit* the new mnemonics when BTI is disabled, this patch will at least make LLVM *accept* assembly code that uses them. Reviewers: pbarrio, tamas.petz, ostannard Reviewed By: pbarrio, ostannard Subscribers: ostannard, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81257
2020-06-09 19:56:30 +02:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+bti < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-bti < %s | FileCheck %s --check-prefix=NOBTI
[AArch64][v8.5A] Add Branch Target Identification instructions This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225
2018-09-27 16:54:33 +02:00
bti
bti c
bti j
bti jc
// CHECK: bti // encoding: [0x1f,0x24,0x03,0xd5]
// CHECK: bti c // encoding: [0x5f,0x24,0x03,0xd5]
// CHECK: bti j // encoding: [0x9f,0x24,0x03,0xd5]
// CHECK: bti jc // encoding: [0xdf,0x24,0x03,0xd5]
[AArch64] Allow BTI mnemonics in the HINT space with BTI disabled Summary: It is important to emit HINT instructions instead of BTI ones when BTI is disabled. This allows compatibility with other assemblers (e.g. GAS). Still, developers of assembly code will want to write code that is compatible with both pre- and post-BTI CPUs. They could use HINT mnemonics, but the new mnemonics are a lot more readable (e.g. bti c instead of hint #34), and they will result in the same encodings. So, while LLVM should not *emit* the new mnemonics when BTI is disabled, this patch will at least make LLVM *accept* assembly code that uses them. Reviewers: pbarrio, tamas.petz, ostannard Reviewed By: pbarrio, ostannard Subscribers: ostannard, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D81257
2020-06-09 19:56:30 +02:00
// NOBTI: hint #32 // encoding: [0x1f,0x24,0x03,0xd5]
// NOBTI: hint #34 // encoding: [0x5f,0x24,0x03,0xd5]
// NOBTI: hint #36 // encoding: [0x9f,0x24,0x03,0xd5]
// NOBTI: hint #38 // encoding: [0xdf,0x24,0x03,0xd5]
[AArch64][v8.5A] Add Branch Target Identification instructions This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225
2018-09-27 16:54:33 +02:00
hint #32
hint #34
hint #36
hint #38
// CHECK: bti // encoding: [0x1f,0x24,0x03,0xd5]
// CHECK: bti c // encoding: [0x5f,0x24,0x03,0xd5]
// CHECK: bti j // encoding: [0x9f,0x24,0x03,0xd5]
// CHECK: bti jc // encoding: [0xdf,0x24,0x03,0xd5]
// NOBTI: hint #32 // encoding: [0x1f,0x24,0x03,0xd5]
// NOBTI: hint #34 // encoding: [0x5f,0x24,0x03,0xd5]
// NOBTI: hint #36 // encoding: [0x9f,0x24,0x03,0xd5]
// NOBTI: hint #38 // encoding: [0xdf,0x24,0x03,0xd5]
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