llvm-mirror/test/TableGen/eqbit.td

mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
// CHECK: a = 6
// CHECK: a = 5

class A<bit b = 1> {
  int a = !if(!eq(b, 1), 5, 6);
}

def X : A<0>;
def Y : A;
s/tblgen/llvm-tblgen/g in a few missed places, including the tests llvm-svn: 141294 2011-10-06 15:39:59 +02:00			`// RUN: llvm-tblgen %s \| FileCheck %s`
let the '!eq' expression support 'int' and 'bit' types llvm-svn: 106171 2010-06-17 01:24:12 +02:00			`// XFAIL: vg_leak`
			`// CHECK: a = 6`
			`// CHECK: a = 5`

			`class A<bit b = 1> {`
			`int a = !if(!eq(b, 1), 5, 6);`
			`}`

			`def X : A<0>;`
			`def Y : A;`