2016-09-22 04:10:37 +02:00
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//===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2016-09-22 04:10:37 +02:00
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by AArch64RegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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2017-01-13 11:53:57 +01:00
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RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
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/* StartIdx, Length, RegBank */
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2017-11-03 00:38:13 +01:00
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// 0: FPR 16-bit value.
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{0, 16, AArch64::FPRRegBank},
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// 1: FPR 32-bit value.
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2017-01-13 11:53:57 +01:00
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{0, 32, AArch64::FPRRegBank},
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2017-11-03 00:38:13 +01:00
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// 2: FPR 64-bit value.
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2017-01-13 11:53:57 +01:00
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{0, 64, AArch64::FPRRegBank},
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2017-11-03 00:38:13 +01:00
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// 3: FPR 128-bit value.
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2017-01-13 11:53:57 +01:00
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{0, 128, AArch64::FPRRegBank},
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2017-11-03 00:38:13 +01:00
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// 4: FPR 256-bit value.
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2017-01-13 11:53:57 +01:00
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{0, 256, AArch64::FPRRegBank},
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2017-11-03 00:38:13 +01:00
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// 5: FPR 512-bit value.
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Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{0, 512, AArch64::FPRRegBank},
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2017-11-03 00:38:13 +01:00
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// 6: GPR 32-bit value.
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Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{0, 32, AArch64::GPRRegBank},
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2017-11-03 00:38:13 +01:00
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// 7: GPR 64-bit value.
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{0, 64, AArch64::GPRRegBank},
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};
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2016-09-30 02:09:58 +02:00
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2016-09-28 00:55:04 +02:00
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// ValueMappings.
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2017-01-13 11:53:57 +01:00
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RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
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2016-12-06 14:55:01 +01:00
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/* BreakDown, NumBreakDowns */
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2017-02-06 22:57:06 +01:00
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// 0: invalid
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{nullptr, 0},
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2016-12-06 14:55:01 +01:00
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// 3-operands instructions (all binary operations should end up with one of
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// those mapping).
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2017-11-03 00:38:13 +01:00
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// 1: FPR 16-bit value. <-- This must match First3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 4: FPR 32-bit value. <-- This must match First3OpsIdx.
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2017-01-13 11:53:57 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 7: FPR 64-bit value.
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2017-01-13 11:53:57 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 10: FPR 128-bit value.
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2017-01-13 11:53:57 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 13: FPR 256-bit value.
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2017-01-13 11:53:57 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 16: FPR 512-bit value.
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2017-01-13 11:53:57 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 19: GPR 32-bit value.
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 22: GPR 64-bit value. <-- This must match Last3OpsIdx.
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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2016-12-06 14:55:01 +01:00
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// Cross register bank copies.
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2017-11-18 05:28:56 +01:00
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// 25: FPR 16-bit value to GPR 16-bit. <-- This must match
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// FirstCrossRegCpyIdx.
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// Note: This is the kind of copy we see with physical registers.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 27: FPR 32-bit value to GPR 32-bit value.
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2017-01-18 15:26:12 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 29: FPR 64-bit value to GPR 64-bit value.
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2017-01-18 15:26:12 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 31: FPR 128-bit value to GPR 128-bit value (invalid)
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{nullptr, 1},
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{nullptr, 1},
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2017-11-03 00:38:13 +01:00
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// 33: FPR 256-bit value to GPR 256-bit value (invalid)
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{nullptr, 1},
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{nullptr, 1},
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2017-11-03 00:38:13 +01:00
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// 35: FPR 512-bit value to GPR 512-bit value (invalid)
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{nullptr, 1},
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{nullptr, 1},
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2017-11-03 00:38:13 +01:00
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// 37: GPR 32-bit value to FPR 32-bit value.
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2017-01-18 15:26:12 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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2017-11-03 00:38:13 +01:00
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// 39: GPR 64-bit value to FPR 64-bit value. <-- This must match
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2016-12-06 14:55:01 +01:00
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// LastCrossRegCpyIdx.
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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2017-01-13 11:53:57 +01:00
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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2017-11-03 00:38:19 +01:00
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// 41: FPExt: 16 to 32. <-- This must match FPExt16To32Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 43: FPExt: 16 to 32. <-- This must match FPExt16To64Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 45: FPExt: 32 to 64. <-- This must match FPExt32To64Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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// 47: FPExt vector: 64 to 128. <-- This must match FPExt64To128Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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2016-09-28 00:55:04 +02:00
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};
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2017-01-13 11:53:57 +01:00
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bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
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unsigned ValStartIdx,
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unsigned ValLength,
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const RegisterBank &RB) {
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const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
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return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
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Map.RegBank == &RB;
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}
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bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
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unsigned FirstInBank,
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unsigned Size,
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unsigned Offset) {
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unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
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const ValueMapping &Map =
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2017-01-13 12:50:34 +01:00
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AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
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2017-01-13 11:53:57 +01:00
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return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
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Map.NumBreakDowns == 1;
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}
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2017-01-13 12:50:34 +01:00
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bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
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PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
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ArrayRef<PartialMappingIdx> Order) {
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if (Order.front() != FirstAlias)
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return false;
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if (Order.back() != LastAlias)
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return false;
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if (Order.front() > Order.back())
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return false;
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PartialMappingIdx Previous = Order.front();
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bool First = true;
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for (const auto &Current : Order) {
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if (First) {
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First = false;
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continue;
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}
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if (Previous + 1 != Current)
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return false;
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Previous = Current;
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}
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return true;
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}
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unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
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unsigned Size) {
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if (RBIdx == PMI_FirstGPR) {
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if (Size <= 32)
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return 0;
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|
if (Size <= 64)
|
|
|
|
return 1;
|
2017-02-06 22:57:06 +01:00
|
|
|
return -1;
|
2017-01-13 12:50:34 +01:00
|
|
|
}
|
|
|
|
if (RBIdx == PMI_FirstFPR) {
|
2017-11-03 00:38:13 +01:00
|
|
|
if (Size <= 16)
|
2017-01-13 12:50:34 +01:00
|
|
|
return 0;
|
2017-11-03 00:38:13 +01:00
|
|
|
if (Size <= 32)
|
2017-01-13 12:50:34 +01:00
|
|
|
return 1;
|
2017-11-03 00:38:13 +01:00
|
|
|
if (Size <= 64)
|
2017-01-13 12:50:34 +01:00
|
|
|
return 2;
|
2017-11-03 00:38:13 +01:00
|
|
|
if (Size <= 128)
|
2017-01-13 12:50:34 +01:00
|
|
|
return 3;
|
2017-11-03 00:38:13 +01:00
|
|
|
if (Size <= 256)
|
2017-01-13 12:50:34 +01:00
|
|
|
return 4;
|
2017-11-03 00:38:13 +01:00
|
|
|
if (Size <= 512)
|
|
|
|
return 5;
|
2017-02-06 22:57:06 +01:00
|
|
|
return -1;
|
2017-01-13 12:50:34 +01:00
|
|
|
}
|
2017-02-06 22:57:06 +01:00
|
|
|
return -1;
|
2017-01-13 12:50:34 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
const RegisterBankInfo::ValueMapping *
|
|
|
|
AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
|
|
|
|
unsigned Size) {
|
|
|
|
assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
|
2017-02-06 22:57:06 +01:00
|
|
|
unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
|
|
|
|
if (BaseIdxOffset == -1u)
|
|
|
|
return &ValMappings[InvalidIdx];
|
|
|
|
|
|
|
|
unsigned ValMappingIdx =
|
|
|
|
First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) *
|
|
|
|
ValueMappingIdx::DistanceBetweenRegBanks;
|
2017-01-13 12:50:34 +01:00
|
|
|
assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
|
|
|
|
"Mapping out of bound");
|
|
|
|
|
|
|
|
return &ValMappings[ValMappingIdx];
|
|
|
|
}
|
|
|
|
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
AArch64GenRegisterBankInfo::PartialMappingIdx
|
|
|
|
AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
|
2017-01-18 15:26:12 +01:00
|
|
|
PMI_None, // CCR
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
PMI_FirstFPR, // FPR
|
|
|
|
PMI_FirstGPR, // GPR
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
};
|
|
|
|
|
2017-01-13 12:50:34 +01:00
|
|
|
const RegisterBankInfo::ValueMapping *
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
|
|
|
|
unsigned SrcBankID, unsigned Size) {
|
|
|
|
assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
|
|
|
|
assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
|
|
|
|
PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
|
|
|
|
PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
|
|
|
|
assert(DstRBIdx != PMI_None && "No such mapping");
|
|
|
|
assert(SrcRBIdx != PMI_None && "No such mapping");
|
|
|
|
|
2017-01-13 12:50:34 +01:00
|
|
|
if (DstRBIdx == SrcRBIdx)
|
|
|
|
return getValueMapping(DstRBIdx, Size);
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
|
2017-01-13 12:50:34 +01:00
|
|
|
assert(Size <= 64 && "GPR cannot handle that size");
|
|
|
|
unsigned ValMappingIdx =
|
|
|
|
FirstCrossRegCpyIdx +
|
|
|
|
(DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
|
|
|
|
ValueMappingIdx::DistanceBetweenCrossRegCpy;
|
|
|
|
assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
|
|
|
|
ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
|
|
|
|
return &ValMappings[ValMappingIdx];
|
|
|
|
}
|
2017-11-03 00:38:19 +01:00
|
|
|
|
|
|
|
const RegisterBankInfo::ValueMapping *
|
|
|
|
AArch64GenRegisterBankInfo::getFPExtMapping(unsigned DstSize,
|
|
|
|
unsigned SrcSize) {
|
|
|
|
// We support:
|
|
|
|
// - For Scalar:
|
|
|
|
// - 16 to 32.
|
|
|
|
// - 16 to 64.
|
|
|
|
// - 32 to 64.
|
|
|
|
// => FPR 16 to FPR 32|64
|
|
|
|
// => FPR 32 to FPR 64
|
|
|
|
// - For vectors:
|
|
|
|
// - v4f16 to v4f32
|
|
|
|
// - v2f32 to v2f64
|
|
|
|
// => FPR 64 to FPR 128
|
|
|
|
|
|
|
|
// Check that we have been asked sensible sizes.
|
|
|
|
if (SrcSize == 16) {
|
|
|
|
assert((DstSize == 32 || DstSize == 64) && "Unexpected half extension");
|
|
|
|
if (DstSize == 32)
|
|
|
|
return &ValMappings[FPExt16To32Idx];
|
|
|
|
return &ValMappings[FPExt16To64Idx];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (SrcSize == 32) {
|
|
|
|
assert(DstSize == 64 && "Unexpected float extension");
|
|
|
|
return &ValMappings[FPExt32To64Idx];
|
|
|
|
}
|
|
|
|
assert((SrcSize == 64 || DstSize == 128) && "Unexpected vector extension");
|
|
|
|
return &ValMappings[FPExt64To128Idx];
|
|
|
|
}
|
2016-09-22 04:10:37 +02:00
|
|
|
} // End llvm namespace.
|