From 001d77720709473044615b1f9968e721a08bce05 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Wed, 22 Jul 2009 22:44:56 +0000 Subject: [PATCH] Rename the new unsigned and signed keywords to nuw and nsw, which stand for no-unsigned-wrap and no-signed-wrap. llvm-svn: 76810 --- docs/LangRef.html | 43 ++++++++-------- lib/AsmParser/LLLexer.cpp | 4 +- lib/AsmParser/LLParser.cpp | 58 +++++++++++----------- lib/AsmParser/LLToken.h | 4 +- lib/VMCore/AsmWriter.cpp | 4 +- test/Assembler/flags-reversed.ll | 12 ++--- test/Assembler/flags-signed.ll | 12 ++--- test/Assembler/flags-unsigned.ll | 12 ++--- test/Assembler/flags.ll | 84 ++++++++++++++++---------------- 9 files changed, 118 insertions(+), 115 deletions(-) diff --git a/docs/LangRef.html b/docs/LangRef.html index bf98e040ca7..57aace82bab 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -2601,9 +2601,9 @@ Instruction
Syntax:
   <result> = add <ty> <op1>, <op2>          ; yields {ty}:result
-  <result> = signed add <ty> <op1>, <op2>   ; yields {ty}:result
-  <result> = unsigned add <ty> <op1>, <op2> ; yields {ty}:result
-  <result> = unsigned signed add <ty> <op1>, <op2> ; yields {ty}:result
+  <result> = nuw add <ty> <op1>, <op2>      ; yields {ty}:result
+  <result> = nsw add <ty> <op1>, <op2>      ; yields {ty}:result
+  <result> = nuw nsw add <ty> <op1>, <op2>  ; yields {ty}:result
Overview:
@@ -2623,9 +2623,10 @@ Instruction

Because LLVM integers use a two's complement representation, this instruction is appropriate for both signed and unsigned integers.

-

If the signed and/or unsigned keywords are present, - the result value of the add is undefined if signed and/or unsigned - overflow, respectively, occurs.

+

nuw and nsw stand for "No Unsigned Wrap" + and "No Signed Wrap", respectively. If the nuw and/or + nsw keywords are present, the result value of the add + is undefined if unsigned and/or signed overflow, respectively, occurs.

Example:
@@ -2673,10 +2674,10 @@ Instruction 
 
 
Syntax:

 
-  <result> = sub <ty> <op1>, <op2>            ; yields {ty}:result
-  <result> = signed sub <ty> <op1>, <op2>     ; yields {ty}:result
-  <result> = unsigned sub <ty> <op1>, <op2>   ; yields {ty}:result
-  <result> = unsigned signed sub <ty> <op1>, <op2>   ; yields {ty}:result
+  <result> = sub <ty> <op1>, <op2>          ; yields {ty}:result
+  <result> = nuw sub <ty> <op1>, <op2>      ; yields {ty}:result
+  <result> = nsw sub <ty> <op1>, <op2>      ; yields {ty}:result
+  <result> = nuw nsw sub <ty> <op1>, <op2>  ; yields {ty}:result
 

 
 
Overview:

@@ -2702,9 +2703,10 @@ Instruction 
 
Because LLVM integers use a two's complement representation, this instruction
    is appropriate for both signed and unsigned integers.

 
-
If the signed and/or unsigned keywords are present,
-   the result value of the sub is undefined if signed and/or unsigned
-   overflow, respectively, occurs.

+
nuw and nsw stand for "No Unsigned Wrap"
+   and "No Signed Wrap", respectively. If the nuw and/or
+   nsw keywords are present, the result value of the sub
+   is undefined if unsigned and/or signed overflow, respectively, occurs.

 
 
Example:

 
@@ -2759,10 +2761,10 @@ Instruction 
 
 
Syntax:

 
-  <result> = mul <ty> <op1>, <op2>            ; yields {ty}:result
-  <result> = signed mul <ty> <op1>, <op2>     ; yields {ty}:result
-  <result> = unsigned mul <ty> <op1>, <op2>   ; yields {ty}:result
-  <result> = unsigned signed mul <ty> <op1>, <op2>   ; yields {ty}:result
+  <result> = mul <ty> <op1>, <op2>          ; yields {ty}:result
+  <result> = nuw mul <ty> <op1>, <op2>      ; yields {ty}:result
+  <result> = nsw mul <ty> <op1>, <op2>      ; yields {ty}:result
+  <result> = nuw nsw mul <ty> <op1>, <op2>  ; yields {ty}:result
 

 
 
Overview:

@@ -2787,9 +2789,10 @@ Instruction 
    be sign-extended or zero-extended as appropriate to the width of the full
    product.

 
-
If the signed and/or unsigned keywords are present,
-   the result value of the mul is undefined if signed and/or unsigned
-   overflow, respectively, occurs.

+
nuw and nsw stand for "No Unsigned Wrap"
+   and "No Signed Wrap", respectively. If the nuw and/or
+   nsw keywords are present, the result value of the mul
+   is undefined if unsigned and/or signed overflow, respectively, occurs.

 
 
Example:

 
diff --git a/lib/AsmParser/LLLexer.cpp b/lib/AsmParser/LLLexer.cpp
index 313213cb487..e047002c138 100644
--- a/lib/AsmParser/LLLexer.cpp
+++ b/lib/AsmParser/LLLexer.cpp
@@ -501,8 +501,8 @@ lltok::Kind LLLexer::LexIdentifier() {
   KEYWORD(deplibs);
   KEYWORD(datalayout);
   KEYWORD(volatile);
-  KEYWORD(signed);
-  KEYWORD(unsigned);
+  KEYWORD(nuw);
+  KEYWORD(nsw);
   KEYWORD(exact);
   KEYWORD(align);
   KEYWORD(addrspace);
diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp
index 9f708a860cf..bb92b16300e 100644
--- a/lib/AsmParser/LLParser.cpp
+++ b/lib/AsmParser/LLParser.cpp
@@ -2045,26 +2045,9 @@ bool LLParser::ParseValID(ValID &ID) {
     ID.Kind = ValID::t_Constant;
     return false;
   }
-  case lltok::kw_signed: {
+  case lltok::kw_nuw: {
     Lex.Lex();
-    bool AlsoUnsigned = EatIfPresent(lltok::kw_unsigned);
-    if (Lex.getKind() != lltok::kw_add &&
-        Lex.getKind() != lltok::kw_sub &&
-        Lex.getKind() != lltok::kw_mul)
-      return TokError("expected 'add', 'sub', or 'mul'");
-    bool Result = LLParser::ParseValID(ID);
-    if (!Result) {
-      cast(ID.ConstantVal)
-        ->setHasNoSignedOverflow(true);
-      if (AlsoUnsigned)
-        cast(ID.ConstantVal)
-          ->setHasNoUnsignedOverflow(true);
-    }
-    return Result;
-  }
-  case lltok::kw_unsigned: {
-    Lex.Lex();
-    bool AlsoSigned = EatIfPresent(lltok::kw_signed);
+    bool AlsoSigned = EatIfPresent(lltok::kw_nsw);
     if (Lex.getKind() != lltok::kw_add &&
         Lex.getKind() != lltok::kw_sub &&
         Lex.getKind() != lltok::kw_mul)
@@ -2079,6 +2062,23 @@ bool LLParser::ParseValID(ValID &ID) {
     }
     return Result;
   }
+  case lltok::kw_nsw: {
+    Lex.Lex();
+    bool AlsoUnsigned = EatIfPresent(lltok::kw_nuw);
+    if (Lex.getKind() != lltok::kw_add &&
+        Lex.getKind() != lltok::kw_sub &&
+        Lex.getKind() != lltok::kw_mul)
+      return TokError("expected 'add', 'sub', or 'mul'");
+    bool Result = LLParser::ParseValID(ID);
+    if (!Result) {
+      cast(ID.ConstantVal)
+        ->setHasNoSignedOverflow(true);
+      if (AlsoUnsigned)
+        cast(ID.ConstantVal)
+          ->setHasNoUnsignedOverflow(true);
+    }
+    return Result;
+  }
   case lltok::kw_exact: {
     Lex.Lex();
     if (Lex.getKind() != lltok::kw_sdiv)
@@ -2609,8 +2609,8 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
       return ParseStore(Inst, PFS, true);
     else
       return TokError("expected 'load' or 'store'");
-  case lltok::kw_signed: {
-    bool AlsoUnsigned = EatIfPresent(lltok::kw_unsigned);
+  case lltok::kw_nuw: {
+    bool AlsoSigned = EatIfPresent(lltok::kw_nsw);
     if (Lex.getKind() == lltok::kw_add ||
         Lex.getKind() == lltok::kw_sub ||
         Lex.getKind() == lltok::kw_mul) {
@@ -2618,16 +2618,16 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
       KeywordVal = Lex.getUIntVal();
       bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 0);
       if (!Result) {
-        cast(Inst)->setHasNoSignedOverflow(true);
-        if (AlsoUnsigned)
-          cast(Inst)->setHasNoUnsignedOverflow(true);
+        cast(Inst)->setHasNoUnsignedOverflow(true);
+        if (AlsoSigned)
+          cast(Inst)->setHasNoSignedOverflow(true);
       }
       return Result;
     }
     return TokError("expected 'add', 'sub', or 'mul'");
   }
-  case lltok::kw_unsigned: {
-    bool AlsoSigned = EatIfPresent(lltok::kw_signed);
+  case lltok::kw_nsw: {
+    bool AlsoUnsigned = EatIfPresent(lltok::kw_nuw);
     if (Lex.getKind() == lltok::kw_add ||
         Lex.getKind() == lltok::kw_sub ||
         Lex.getKind() == lltok::kw_mul) {
@@ -2635,9 +2635,9 @@ bool LLParser::ParseInstruction(Instruction *&Inst, BasicBlock *BB,
       KeywordVal = Lex.getUIntVal();
       bool Result = ParseArithmetic(Inst, PFS, KeywordVal, 1);
       if (!Result) {
-        cast(Inst)->setHasNoUnsignedOverflow(true);
-        if (AlsoSigned)
-          cast(Inst)->setHasNoSignedOverflow(true);
+        cast(Inst)->setHasNoSignedOverflow(true);
+        if (AlsoUnsigned)
+          cast(Inst)->setHasNoUnsignedOverflow(true);
       }
       return Result;
     }
diff --git a/lib/AsmParser/LLToken.h b/lib/AsmParser/LLToken.h
index b78a09d43e2..c8cdff6bf61 100644
--- a/lib/AsmParser/LLToken.h
+++ b/lib/AsmParser/LLToken.h
@@ -51,8 +51,8 @@ namespace lltok {
     kw_deplibs,
     kw_datalayout,
     kw_volatile,
-    kw_signed,
-    kw_unsigned,
+    kw_nuw,
+    kw_nsw,
     kw_exact,
     kw_align,
     kw_addrspace,
diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp
index 6e84af3211c..d9d8cc834d5 100644
--- a/lib/VMCore/AsmWriter.cpp
+++ b/lib/VMCore/AsmWriter.cpp
@@ -856,9 +856,9 @@ static void WriteOptimizationInfo(raw_ostream &Out, const User *U) {
   if (const OverflowingBinaryOperator *OBO =
         dyn_cast(U)) {
     if (OBO->hasNoUnsignedOverflow())
-      Out << "unsigned ";
+      Out << "nuw ";
     if (OBO->hasNoSignedOverflow())
-      Out << "signed ";
+      Out << "nsw ";
   } else if (const SDivOperator *Div = dyn_cast(U)) {
     if (Div->isExact())
       Out << "exact ";
diff --git a/test/Assembler/flags-reversed.ll b/test/Assembler/flags-reversed.ll
index b63ac849537..d66095a5c3f 100644
--- a/test/Assembler/flags-reversed.ll
+++ b/test/Assembler/flags-reversed.ll
@@ -3,16 +3,16 @@
 @addr = external global i64
 
 define i64 @add_both_reversed_ce() {
-; CHECK: ret i64 unsigned signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sub_both_reversed_ce() {
-; CHECK: ret i64 unsigned signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @mul_both_reversed_ce() {
-; CHECK: ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
diff --git a/test/Assembler/flags-signed.ll b/test/Assembler/flags-signed.ll
index 136dd57dd83..62c38a92006 100644
--- a/test/Assembler/flags-signed.ll
+++ b/test/Assembler/flags-signed.ll
@@ -3,16 +3,16 @@
 @addr = external global i64
 
 define i64 @add_signed_ce() {
-; CHECK: ret i64 signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sub_signed_ce() {
-; CHECK: ret i64 signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @mul_signed_ce() {
-; CHECK: ret i64 signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
diff --git a/test/Assembler/flags-unsigned.ll b/test/Assembler/flags-unsigned.ll
index 1526db0770d..cd051af23f5 100644
--- a/test/Assembler/flags-unsigned.ll
+++ b/test/Assembler/flags-unsigned.ll
@@ -3,16 +3,16 @@
 @addr = external global i64
 
 define i64 @add_unsigned_ce() {
-; CHECK: ret i64 unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sub_unsigned_ce() {
-; CHECK: ret i64 unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @mul_unsigned_ce() {
-; CHECK: ret i64 unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 unsigned mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nuw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
diff --git a/test/Assembler/flags.ll b/test/Assembler/flags.ll
index 317bc0cf1c6..a0c2abce27d 100644
--- a/test/Assembler/flags.ll
+++ b/test/Assembler/flags.ll
@@ -2,39 +2,39 @@
 
 @addr = external global i64
 
-define i64 @add_signed(i64 %x, i64 %y) {
-; CHECK: %z = signed add i64 %x, %y
-	%z = signed add i64 %x, %y
-	ret i64 %z
-}
-
-define i64 @sub_signed(i64 %x, i64 %y) {
-; CHECK: %z = signed sub i64 %x, %y
-	%z = signed sub i64 %x, %y
-	ret i64 %z
-}
-
-define i64 @mul_signed(i64 %x, i64 %y) {
-; CHECK: %z = signed mul i64 %x, %y
-	%z = signed mul i64 %x, %y
-	ret i64 %z
-}
-
 define i64 @add_unsigned(i64 %x, i64 %y) {
-; CHECK: %z = unsigned add i64 %x, %y
-	%z = unsigned add i64 %x, %y
+; CHECK: %z = nuw add i64 %x, %y
+	%z = nuw add i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @sub_unsigned(i64 %x, i64 %y) {
-; CHECK: %z = unsigned sub i64 %x, %y
-	%z = unsigned sub i64 %x, %y
+; CHECK: %z = nuw sub i64 %x, %y
+	%z = nuw sub i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @mul_unsigned(i64 %x, i64 %y) {
-; CHECK: %z = unsigned mul i64 %x, %y
-	%z = unsigned mul i64 %x, %y
+; CHECK: %z = nuw mul i64 %x, %y
+	%z = nuw mul i64 %x, %y
+	ret i64 %z
+}
+
+define i64 @add_signed(i64 %x, i64 %y) {
+; CHECK: %z = nsw add i64 %x, %y
+	%z = nsw add i64 %x, %y
+	ret i64 %z
+}
+
+define i64 @sub_signed(i64 %x, i64 %y) {
+; CHECK: %z = nsw sub i64 %x, %y
+	%z = nsw sub i64 %x, %y
+	ret i64 %z
+}
+
+define i64 @mul_signed(i64 %x, i64 %y) {
+; CHECK: %z = nsw mul i64 %x, %y
+	%z = nsw mul i64 %x, %y
 	ret i64 %z
 }
 
@@ -57,38 +57,38 @@ define i64 @mul_plain(i64 %x, i64 %y) {
 }
 
 define i64 @add_both(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed add i64 %x, %y
-	%z = unsigned signed add i64 %x, %y
+; CHECK: %z = nuw nsw add i64 %x, %y
+	%z = nuw nsw add i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @sub_both(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed sub i64 %x, %y
-	%z = unsigned signed sub i64 %x, %y
+; CHECK: %z = nuw nsw sub i64 %x, %y
+	%z = nuw nsw sub i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @mul_both(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed mul i64 %x, %y
-	%z = unsigned signed mul i64 %x, %y
+; CHECK: %z = nuw nsw mul i64 %x, %y
+	%z = nuw nsw mul i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @add_both_reversed(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed add i64 %x, %y
-	%z = signed unsigned add i64 %x, %y
+; CHECK: %z = nuw nsw add i64 %x, %y
+	%z = nsw nuw add i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @sub_both_reversed(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed sub i64 %x, %y
-	%z = signed unsigned sub i64 %x, %y
+; CHECK: %z = nuw nsw sub i64 %x, %y
+	%z = nsw nuw sub i64 %x, %y
 	ret i64 %z
 }
 
 define i64 @mul_both_reversed(i64 %x, i64 %y) {
-; CHECK: %z = unsigned signed mul i64 %x, %y
-	%z = signed unsigned mul i64 %x, %y
+; CHECK: %z = nuw nsw mul i64 %x, %y
+	%z = nsw nuw mul i64 %x, %y
 	ret i64 %z
 }
 
@@ -105,18 +105,18 @@ define i64 @sdiv_plain(i64 %x, i64 %y) {
 }
 
 define i64 @add_both_ce() {
-; CHECK: ret i64 unsigned signed add (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed unsigned add (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw add (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw nuw add (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sub_both_ce() {
-; CHECK: ret i64 unsigned signed sub (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 signed unsigned sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nsw nuw sub (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @mul_both_ce() {
-; CHECK: ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
-	ret i64 unsigned signed mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+; CHECK: ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
+	ret i64 nuw nsw mul (i64 ptrtoint (i64* @addr to i64), i64 91)
 }
 
 define i64 @sdiv_exact_ce() {