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[SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes

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This patch fixes a codegen crash introduced in fde24661718c, where the
DAGCombiner started generating optimized MULH[SU] or [SU]MUL_LOHI nodes
unless the target opted out. The AArch64 backend cannot currently select
any of these nodes, so ensure that they are not generated in the first
place.

This issue was raised by @huihuiz in D94501.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D96849
This commit is contained in:
Fraser Cormack 2021-02-17 09:25:58 +00:00
parent 78cda129f4
commit 0099d58a88
2 changed files with 29 additions and 0 deletions
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5
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -1124,6 +1124,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
setOperationAction(ISD::MULHU, VT, Expand);
setOperationAction(ISD::MULHS, VT, Expand);
setOperationAction(ISD::UMUL_LOHI, VT, Expand);
setOperationAction(ISD::SMUL_LOHI, VT, Expand);
}
// Illegal unpacked integer vector types.

24
test/CodeGen/AArch64/sve-int-arith-imm.ll
View File

@ -779,3 +779,27 @@ define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){
%lshr = lshr <vscale x 2 x i64> %a, %splat
ret <vscale x 2 x i64> %lshr
}
define <vscale x 4 x i32> @sdiv_const(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sdiv_const:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z1.s, #3 // =0x3
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
entry:
%div = sdiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
ret <vscale x 4 x i32> %div
}
define <vscale x 4 x i32> @udiv_const(<vscale x 4 x i32> %a) {
; CHECK-LABEL: udiv_const:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov z1.s, #3 // =0x3
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: ret
entry:
%div = udiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
ret <vscale x 4 x i32> %div
}