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AMDGPU: Fold readlane intrinsics of constants

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I'm not 100% sure about this, since I'm worried about IR transforms
that might end up introducing divergence downstream once replaced with
a constant, but I haven't come up with an example yet.

llvm-svn: 363406
This commit is contained in:
Matt Arsenault 2019-06-14 14:51:26 +00:00
parent ec507e9c0b
commit 009f0f6078
2 changed files with 63 additions and 0 deletions
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7
lib/Transforms/InstCombine/InstCombineCalls.cpp
View File

@ -3776,6 +3776,13 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
II->setOperand(0, UndefValue::get(Old->getType()));
return II;
}
case Intrinsic::amdgcn_readfirstlane:
case Intrinsic::amdgcn_readlane: {
// A constant value is trivially uniform.
if (Constant *C = dyn_cast<Constant>(II->getArgOperand(0)))
return replaceInstUsesWith(*II, C);
break;
}
case Intrinsic::stackrestore: {
// If the save is right next to the restore, remove the restore. This can
// happen when variable allocas are DCE'd.

56
test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
View File

@ -2431,6 +2431,62 @@ define void @kill_true() {
ret void
}
; --------------------------------------------------------------------
; llvm.amdgcn.readfirstlane
; --------------------------------------------------------------------
declare i32 @llvm.amdgcn.readfirstlane(i32)
@gv = constant i32 0
define amdgpu_kernel void @readfirstlane_constant(i32 %arg) {
; CHECK-LABEL: @readfirstlane_constant(
; CHECK-NEXT: %var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)
; CHECK-NEXT: store volatile i32 %var, i32* undef, align 4
; CHECK-NEXT: store volatile i32 0, i32* undef, align 4
; CHECK-NEXT: store volatile i32 123, i32* undef, align 4
; CHECK-NEXT: store volatile i32 ptrtoint (i32* @gv to i32), i32* undef, align 4
; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4
%var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)
%zero = call i32 @llvm.amdgcn.readfirstlane(i32 0)
%imm = call i32 @llvm.amdgcn.readfirstlane(i32 123)
%constexpr = call i32 @llvm.amdgcn.readfirstlane(i32 ptrtoint (i32* @gv to i32))
%undef = call i32 @llvm.amdgcn.readfirstlane(i32 undef)
store volatile i32 %var, i32* undef
store volatile i32 %zero, i32* undef
store volatile i32 %imm, i32* undef
store volatile i32 %constexpr, i32* undef
store volatile i32 %undef, i32* undef
ret void
}
; --------------------------------------------------------------------
; llvm.amdgcn.readlane
; --------------------------------------------------------------------
declare i32 @llvm.amdgcn.readlane(i32, i32)
define amdgpu_kernel void @readlane_constant(i32 %arg, i32 %lane) {
; CHECK-LABEL: @readlane_constant(
; CHECK-NEXT: %var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7)
; CHECK-NEXT: store volatile i32 %var, i32* undef, align 4
; CHECK-NEXT: store volatile i32 0, i32* undef, align 4
; CHECK-NEXT: store volatile i32 123, i32* undef, align 4
; CHECK-NEXT: store volatile i32 ptrtoint (i32* @gv to i32), i32* undef, align 4
; CHECK-NEXT: store volatile i32 undef, i32* undef, align 4
%var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7)
%zero = call i32 @llvm.amdgcn.readlane(i32 0, i32 %lane)
%imm = call i32 @llvm.amdgcn.readlane(i32 123, i32 %lane)
%constexpr = call i32 @llvm.amdgcn.readlane(i32 ptrtoint (i32* @gv to i32), i32 %lane)
%undef = call i32 @llvm.amdgcn.readlane(i32 undef, i32 %lane)
store volatile i32 %var, i32* undef
store volatile i32 %zero, i32* undef
store volatile i32 %imm, i32* undef
store volatile i32 %constexpr, i32* undef
store volatile i32 %undef, i32* undef
ret void
}
; --------------------------------------------------------------------
; llvm.amdgcn.update.dpp.i32
; --------------------------------------------------------------------