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[VectorCombine] early exit if target has no vector registers

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Based on post-commit discussion in:
D81766

Other vectorization passes (SLP and Loop) use this TTI API similarly.
This commit is contained in:
Sanjay Patel 2020-08-12 09:20:59 -04:00
parent 575e40e45d
commit 00ebcf5eea
2 changed files with 10 additions and 3 deletions
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4
lib/Transforms/Vectorize/VectorCombine.cpp
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@ -670,6 +670,10 @@ bool VectorCombine::run() {
if (DisableVectorCombine)
return false;
// Don't attempt vectorization if the target does not support vectors.
if (!TTI.getNumberOfRegisters(TTI.getRegisterClassForType(/*Vector*/ true)))
return false;
bool MadeChange = false;
for (BasicBlock &BB : F) {
// Ignore unreachable basic blocks.

9
test/Transforms/VectorCombine/X86/no-sse.ll
View File

@ -1,9 +1,12 @@
; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=-sse | FileCheck %s --check-prefixes=CHECK
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=-sse | FileCheck %s
; Don't spend time on vector transforms if the target does not support vectors.
define <4 x float> @bitcast_shuf_same_size(<4 x i32> %v) {
; CHECK-LABEL: @bitcast_shuf_same_size(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V:%.*]] to <4 x float>
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <4 x float>
; CHECK-NEXT: ret <4 x float> [[R]]
;
%shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>