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[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang

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This patch implements the vec_cntm function prototypes in altivec.h in order to
utilize the vector count mask bits instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82726
This commit is contained in:
Amy Kwan 2020-09-16 10:03:17 -05:00
parent eab425518c
commit 00f4e38665
3 changed files with 67 additions and 4 deletions
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14
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -467,6 +467,20 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
def int_ppc_altivec_vexpandqm : GCCBuiltin<"__builtin_altivec_vexpandqm">,
Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty], [IntrNoMem]>;
// P10 Vector Count with Mask intrinsics.
def int_ppc_altivec_vcntmbb : GCCBuiltin<"__builtin_altivec_vcntmbb">,
Intrinsic<[llvm_i64_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
def int_ppc_altivec_vcntmbh : GCCBuiltin<"__builtin_altivec_vcntmbh">,
Intrinsic<[llvm_i64_ty], [llvm_v8i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
def int_ppc_altivec_vcntmbw : GCCBuiltin<"__builtin_altivec_vcntmbw">,
Intrinsic<[llvm_i64_ty], [llvm_v4i32_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
def int_ppc_altivec_vcntmbd : GCCBuiltin<"__builtin_altivec_vcntmbd">,
Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<1>>]>;
// P10 Vector Parallel Bits Deposit/Extract Doubleword Builtins.
def int_ppc_altivec_vpdepd : GCCBuiltin<"__builtin_altivec_vpdepd">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],

12
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -1046,19 +1046,23 @@ let Predicates = [IsISA3_1] in {
def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
(ins vrrc:$vB, u1imm:$MP),
"vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
[]>;
[(set i64:$rD, (int_ppc_altivec_vcntmbb
v16i8:$vB, timm:$MP))]>;
def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD),
(ins vrrc:$vB, u1imm:$MP),
"vcntmbh $rD, $vB, $MP", IIC_VecGeneral,
[]>;
[(set i64:$rD, (int_ppc_altivec_vcntmbh
v8i16:$vB, timm:$MP))]>;
def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD),
(ins vrrc:$vB, u1imm:$MP),
"vcntmbw $rD, $vB, $MP", IIC_VecGeneral,
[]>;
[(set i64:$rD, (int_ppc_altivec_vcntmbw
v4i32:$vB, timm:$MP))]>;
def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD),
(ins vrrc:$vB, u1imm:$MP),
"vcntmbd $rD, $vB, $MP", IIC_VecGeneral,
[]>;
[(set i64:$rD, (int_ppc_altivec_vcntmbd
v2i64:$vB, timm:$MP))]>;
def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC),
"vextdubvlx $vD, $vA, $vB, $rC",

45
test/CodeGen/PowerPC/p10-vector-mask-ops.ll
View File

@ -120,3 +120,48 @@ entry:
%exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a)
ret <1 x i128> %exp
}
declare i64 @llvm.ppc.altivec.vcntmbb(<16 x i8>, i32)
declare i64 @llvm.ppc.altivec.vcntmbh(<8 x i16>, i32)
declare i64 @llvm.ppc.altivec.vcntmbw(<4 x i32>, i32)
declare i64 @llvm.ppc.altivec.vcntmbd(<2 x i64>, i32)
define i64 @test_vcntmbb(<16 x i8> %a) {
; CHECK-LABEL: test_vcntmbb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vcntmbb r3, v2, 1
; CHECK-NEXT: blr
entry:
%cnt = tail call i64 @llvm.ppc.altivec.vcntmbb(<16 x i8> %a, i32 1)
ret i64 %cnt
}
define i64 @test_vcntmbh(<8 x i16> %a) {
; CHECK-LABEL: test_vcntmbh:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vcntmbh r3, v2, 0
; CHECK-NEXT: blr
entry:
%cnt = tail call i64 @llvm.ppc.altivec.vcntmbh(<8 x i16> %a, i32 0)
ret i64 %cnt
}
define i64 @test_vcntmbw(<4 x i32> %a) {
; CHECK-LABEL: test_vcntmbw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vcntmbw r3, v2, 1
; CHECK-NEXT: blr
entry:
%cnt = tail call i64 @llvm.ppc.altivec.vcntmbw(<4 x i32> %a, i32 1)
ret i64 %cnt
}
define i64 @test_vcntmbd(<2 x i64> %a) {
; CHECK-LABEL: test_vcntmbd:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vcntmbd r3, v2, 0
; CHECK-NEXT: blr
entry:
%cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0)
ret i64 %cnt
}