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[MCA] [In-order pipeline] Fix for 0 latency instruction causing assertion to fail.

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0 latency instructions now get processed and retired properly within the in-order pipeline. Had to fix a bug within TimelineView.cpp as well that would show up when a 0 latency instruction was the first instruction in the source.

Differential Revision: https://reviews.llvm.org/D104675
This commit is contained in:
Patrick Holland 2021-06-20 19:12:00 -07:00
parent daaa1d32d1
commit 0114258120
2 changed files with 12 additions and 2 deletions
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12
lib/MCA/Stages/InOrderIssueStage.cpp
View File

@ -241,6 +241,18 @@ llvm::Error InOrderIssueStage::tryIssue(InstRef &IR) {
Bandwidth = Desc.EndGroup ? 0 : Bandwidth - NumMicroOps; Bandwidth = Desc.EndGroup ? 0 : Bandwidth - NumMicroOps;
} }
// If the instruction has a latency of 0, we need to handle
// the execution and retirement now.
if (IS.isExecuted()) {
PRF.onInstructionExecuted(&IS);
notifyEvent<HWInstructionEvent>(
HWInstructionEvent(HWInstructionEvent::Executed, IR));
LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR << " is executed\n");
retireInstruction(IR);
return llvm::ErrorSuccess();
}
IssuedInst.push_back(IR); IssuedInst.push_back(IR);
if (!IR.getInstruction()->getDesc().RetireOOO) if (!IR.getInstruction()->getDesc().RetireOOO)

2
tools/llvm-mca/Views/TimelineView.cpp
View File

@ -288,8 +288,6 @@ void TimelineView::printTimeline(raw_ostream &OS) const {
for (unsigned Iteration = 0; Iteration < Iterations; ++Iteration) { for (unsigned Iteration = 0; Iteration < Iterations; ++Iteration) {
for (const MCInst &Inst : Source) { for (const MCInst &Inst : Source) {
const TimelineViewEntry &Entry = Timeline[IID]; const TimelineViewEntry &Entry = Timeline[IID];
if (Entry.CycleRetired == 0)
return;
unsigned SourceIndex = IID % Source.size(); unsigned SourceIndex = IID % Source.size();
printTimelineViewEntry(FOS, Entry, Iteration, SourceIndex); printTimelineViewEntry(FOS, Entry, Iteration, SourceIndex);