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[AMDGPU] Fix ds combine with subregs
Differential Revision: https://reviews.llvm.org/D52522 llvm-svn: 343047
This commit is contained in:
Stanislav Mekhanoshin
parent
f8c4c3a58a
commit
011d08c69a
@ -514,6 +514,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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DebugLoc DL = CI.I->getDebugLoc();
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DebugLoc DL = CI.I->getDebugLoc();
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unsigned BaseReg = AddrReg->getReg();
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unsigned BaseReg = AddrReg->getReg();
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unsigned BaseSubReg = AddrReg->getSubReg();
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unsigned BaseRegFlags = 0;
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unsigned BaseRegFlags = 0;
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if (CI.BaseOff) {
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if (CI.BaseOff) {
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unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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@ -525,15 +526,16 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
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TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
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.addReg(ImmReg)
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.addReg(ImmReg)
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.addReg(AddrReg->getReg());
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.addReg(AddrReg->getReg(), 0, BaseSubReg);
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BaseSubReg = 0;
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}
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}
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MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
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MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
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.addReg(BaseReg, BaseRegFlags) // addr
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.addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset1) // offset1
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.addImm(NewOffset1) // offset1
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.addImm(0) // gds
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.addImm(0) // gds
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.cloneMergedMemRefs({&*CI.I, &*CI.Paired});
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.cloneMergedMemRefs({&*CI.I, &*CI.Paired});
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(void)Read2;
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(void)Read2;
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@ -601,6 +603,7 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
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DebugLoc DL = CI.I->getDebugLoc();
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DebugLoc DL = CI.I->getDebugLoc();
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unsigned BaseReg = AddrReg->getReg();
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unsigned BaseReg = AddrReg->getReg();
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unsigned BaseSubReg = AddrReg->getSubReg();
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unsigned BaseRegFlags = 0;
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unsigned BaseRegFlags = 0;
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if (CI.BaseOff) {
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if (CI.BaseOff) {
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unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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unsigned ImmReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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@ -612,17 +615,18 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
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TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
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TII->getAddNoCarry(*MBB, CI.Paired, DL, BaseReg)
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.addReg(ImmReg)
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.addReg(ImmReg)
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.addReg(AddrReg->getReg());
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.addReg(AddrReg->getReg(), 0, BaseSubReg);
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BaseSubReg = 0;
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}
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}
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MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc)
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MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc)
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.addReg(BaseReg, BaseRegFlags) // addr
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.addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
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.add(*Data0) // data0
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.add(*Data0) // data0
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.add(*Data1) // data1
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.add(*Data1) // data1
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset0) // offset0
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.addImm(NewOffset1) // offset1
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.addImm(NewOffset1) // offset1
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.addImm(0) // gds
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.addImm(0) // gds
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.cloneMergedMemRefs({&*CI.I, &*CI.Paired});
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.cloneMergedMemRefs({&*CI.I, &*CI.Paired});
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moveInstsAfter(Write2, CI.InstsToMove);
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moveInstsAfter(Write2, CI.InstsToMove);
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@ -6,7 +6,7 @@
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# $vcc, which is used in _e32); this ensures that $vcc is not inadvertently
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# $vcc, which is used in _e32); this ensures that $vcc is not inadvertently
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# clobbered.
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# clobbered.
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# GCN-LABEL: name: kernel
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# GCN-LABEL: name: ds_combine_base_offset{{$}}
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# VI: V_ADD_I32_e64 %6, %0,
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# VI: V_ADD_I32_e64 %6, %0,
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# VI-NEXT: DS_WRITE2_B32 killed %7, %0, %3, 0, 8,
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# VI-NEXT: DS_WRITE2_B32 killed %7, %0, %3, 0, 8,
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@ -21,7 +21,37 @@
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--- |
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--- |
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@0 = internal unnamed_addr addrspace(3) global [256 x float] undef, align 4
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@0 = internal unnamed_addr addrspace(3) global [256 x float] undef, align 4
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define amdgpu_kernel void @kernel() {
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define amdgpu_kernel void @ds_combine_base_offset() {
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bb.0:
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br label %bb2
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bb1:
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ret void
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bb2:
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%tmp = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @0, i32 0, i32 0
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%tmp1 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 8
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%tmp2 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 16
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%tmp3 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 24
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br label %bb1
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}
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define amdgpu_kernel void @ds_combine_base_offset_subreg() {
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bb.0:
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br label %bb2
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bb1:
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ret void
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bb2:
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%tmp = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @0, i32 0, i32 0
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%tmp1 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 8
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%tmp2 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 16
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%tmp3 = getelementptr inbounds float, float addrspace(3)* %tmp, i32 24
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br label %bb1
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}
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define amdgpu_kernel void @ds_combine_subreg() {
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bb.0:
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bb.0:
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br label %bb2
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br label %bb2
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@ -36,7 +66,7 @@
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br label %bb1
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br label %bb1
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}
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}
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---
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---
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name: kernel
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name: ds_combine_base_offset
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body: |
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body: |
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bb.0:
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%0:vgpr_32 = IMPLICIT_DEF
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@ -58,3 +88,69 @@ body: |
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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S_BRANCH %bb.1
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S_BRANCH %bb.1
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...
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...
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# GCN-LABEL: name: ds_combine_base_offset_subreg{{$}}
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# VI: V_ADD_I32_e64 %6, %0.sub0,
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# VI-NEXT: DS_WRITE2_B32 killed %7, %0.sub0, %3.sub0, 0, 8,
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# VI: V_ADD_I32_e64 %10, %3.sub0,
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# VI-NEXT: DS_READ2_B32 killed %11, 0, 8,
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# GFX9: V_ADD_U32_e64 %6, %0.sub0,
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# GFX9-NEXT: DS_WRITE2_B32_gfx9 killed %7, %0.sub0, %3.sub0, 0, 8,
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# GFX9: V_ADD_U32_e64 %9, %3.sub0,
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# GFX9-NEXT: DS_READ2_B32_gfx9 killed %10, 0, 8,
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---
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name: ds_combine_base_offset_subreg
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body: |
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bb.0:
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%0:vreg_64 = IMPLICIT_DEF
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S_BRANCH %bb.2
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bb.1:
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S_ENDPGM
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bb.2:
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%1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec
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%2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
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V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
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DS_WRITE_B32 %0.sub0, %0.sub0, 1024, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
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undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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DS_WRITE_B32 %0.sub0, %3.sub0, 1056, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)
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%4:vgpr_32 = DS_READ_B32 %3.sub0, 1088, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp2)
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%5:vgpr_32 = DS_READ_B32 %3.sub0, 1120, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp3)
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$vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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S_BRANCH %bb.1
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...
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# GCN-LABEL: name: ds_combine_subreg{{$}}
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# VI: DS_WRITE2_B32 %0.sub0, %0.sub0, %3.sub0, 0, 8,
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# VI: DS_READ2_B32 %3.sub0, 0, 8,
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# GFX9: DS_WRITE2_B32_gfx9 %0.sub0, %0.sub0, %3.sub0, 0, 8,
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# GFX9: DS_READ2_B32_gfx9 %3.sub0, 0, 8,
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---
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name: ds_combine_subreg
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body: |
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bb.0:
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%0:vreg_64 = IMPLICIT_DEF
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S_BRANCH %bb.2
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bb.1:
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S_ENDPGM
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bb.2:
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%1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec
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%2:vgpr_32 = V_CNDMASK_B32_e64 0, 1, %1, implicit $exec
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V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec
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DS_WRITE_B32 %0.sub0, %0.sub0, 0, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp)
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undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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DS_WRITE_B32 %0.sub0, %3.sub0, 32, 0, implicit $m0, implicit $exec :: (store 4 into %ir.tmp1)
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%4:vgpr_32 = DS_READ_B32 %3.sub0, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp2)
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%5:vgpr_32 = DS_READ_B32 %3.sub0, 32, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp3)
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$vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
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S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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S_BRANCH %bb.1
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...
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