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Add implicit def / use operands to MachineInstr.

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llvm-svn: 31633
This commit is contained in:
Evan Cheng 2006-11-10 08:43:01 +00:00
parent b5ca73688b
commit 013597778d
6 changed files with 24 additions and 30 deletions
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9
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -658,16 +658,9 @@ void LiveIntervals::computeIntervals() {
}
for (; MI != miEnd; ++MI) {
const TargetInstrDescriptor &TID = tii_->get(MI->getOpcode());
DEBUG(std::cerr << MIIndex << "\t" << *MI);
// Handle implicit defs.
if (TID.ImplicitDefs) {
for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef)
handleRegisterDef(MBB, MI, MIIndex, *ImpDef);
}
// Handle explicit defs.
// Handle defs.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals

19
lib/CodeGen/LiveVariables.cpp
View File

@ -228,7 +228,6 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
MachineInstr *MI = I;
const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
// Process all of the operands of the instruction...
unsigned NumOperandsToProcess = MI->getNumOperands();
@ -238,14 +237,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
if (MID.ImplicitUses) {
for (const unsigned *ImplicitUses = MID.ImplicitUses;
*ImplicitUses; ++ImplicitUses)
HandlePhysRegUse(*ImplicitUses, MI);
}
// Process all explicit uses...
// Process all uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
@ -258,14 +250,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
}
}
// Loop over implicit defs, defining them.
if (MID.ImplicitDefs) {
for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
*ImplicitDefs; ++ImplicitDefs)
HandlePhysRegDef(*ImplicitDefs, MI);
}
// Process all explicit defs...
// Process all defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg()) {

8
lib/CodeGen/MachineInstr.cpp
View File

@ -205,8 +205,12 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
OS << " ";
::print(mop, OS, TM);
if (mop.isReg() && mop.isDef())
OS << "<def>";
if (mop.isReg()) {
if (mop.isImplicit())
OS << (mop.isDef() ? "<imp-def>" : "<imp-use>");
else if (mop.isDef())
OS << "<def>";
}
}
OS << "\n";

4
lib/CodeGen/RegAllocLocal.cpp
View File

@ -561,7 +561,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
if (MO.isRegister() && !MO.isDef() && !MO.isImplicit() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
@ -596,7 +596,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg() &&
if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
MRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.

12
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -441,6 +441,18 @@ void ScheduleDAG::EmitNode(SDNode *Node,
}
}
// Emit implicit def / use operands.
if (II.ImplicitDefs) {
for (const unsigned *ImplicitDefs = II.ImplicitDefs;
*ImplicitDefs; ++ImplicitDefs)
MI->addRegOperand(*ImplicitDefs, true, true);
}
if (II.ImplicitUses) {
for (const unsigned *ImplicitUses = II.ImplicitUses;
*ImplicitUses; ++ImplicitUses)
MI->addRegOperand(*ImplicitUses, false, true);
}
// Now that we have emitted all operands, emit this instruction itself.
if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
BB->insert(BB->end(), MI);

2
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -196,7 +196,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
assert(MO.isReg() && "Expected to fold into reg operand!");
MIB = addFrameReference(MIB, FrameIndex);
} else if (MO.isReg())
MIB = MIB.addReg(MO.getReg(), MO.isDef());
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
else if (MO.isImm())
MIB = MIB.addImm(MO.getImm());
else if (MO.isGlobalAddress())