RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

Clean up rules

Browse Source 
llvm-svn: 11956
This commit is contained in:
Chris Lattner 2004-02-28 19:43:40 +00:00
parent d2bb7e91b0
commit 013aa47975
1 changed files with 15 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
lib/Target/SparcV8/Makefile
View File

@ -10,46 +10,37 @@ LEVEL = ../../..
LIBRARYNAME = sparcv8
include $(LEVEL)/Makefile.common
TDFILES := $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
TDFILE := $(SourceDir)/SparcV8.td
# Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
$(SourceDir)/SparcV8Reg.td \
$(SourceDir)/../Target.td $(TBLGEN)
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-enums -o $@
SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
$(SourceDir)/SparcV8Reg.td \
$(SourceDir)/../Target.td $(TBLGEN)
SparcV8GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register information header with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc-header -o $@
SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
$(SourceDir)/SparcV8Reg.td \
$(SourceDir)/../Target.td $(TBLGEN)
SparcV8GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register information implementation with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc -o $@
SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
$(SourceDir)/SparcV8Instrs.td \
$(SourceDir)/../Target.td $(TBLGEN)
SparcV8GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-enums -o $@
SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
$(SourceDir)/SparcV8Instrs.td \
$(SourceDir)/../Target.td $(TBLGEN)
SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
$(SourceDir)/SparcV8Instrs.td \
$(SourceDir)/../Target.td $(TBLGEN)
SparcV8GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction selector with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-selector -o $@
clean::
$(VERB) rm -f *.inc