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Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

Browse Source 
This reapplies commit r352010 with RISC-V test fixes.

llvm-svn: 352237
This commit is contained in:
Ana Pazos 2019-01-25 20:22:49 +00:00
parent 49bf5cf617
commit 015647cf0a
12 changed files with 1602 additions and 2142 deletions
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13
lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@ -447,3 +447,16 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
}
}
}
bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
const unsigned Opcode = MI.getOpcode();
switch(Opcode) {
default:
break;
case RISCV::ADDI:
case RISCV::ORI:
case RISCV::XORI:
return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
}
return MI.isAsCheapAsAMove();
}

2
lib/Target/RISCV/RISCVInstrInfo.h
View File

@ -78,6 +78,8 @@ public:
bool isBranchOffsetInRange(unsigned BranchOpc,
int64_t BrOffset) const override;
bool isAsCheapAsAMove(const MachineInstr &MI) const override;
};
}
#endif

6
lib/Target/RISCV/RISCVInstrInfo.td
View File

@ -315,7 +315,7 @@ class Priv<string opcodestr, bits<7> funct7>
//===----------------------------------------------------------------------===//
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
let isReMaterializable = 1 in
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def LUI : RVInstU<OPC_LUI, (outs GPR:$rd), (ins uimm20_lui:$imm20),
"lui", "$rd, $imm20">;
@ -351,13 +351,13 @@ def SW : Store_rri<0b010, "sw">;
// ADDI isn't always rematerializable, but isReMaterializable will be used as
// a hint which is verified in isReallyTriviallyReMaterializable.
let isReMaterializable = 1 in
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
def ADDI : ALU_ri<0b000, "addi">;
def SLTI : ALU_ri<0b010, "slti">;
def SLTIU : ALU_ri<0b011, "sltiu">;
let isReMaterializable = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def XORI : ALU_ri<0b100, "xori">;
def ORI : ALU_ri<0b110, "ori">;
}

114
test/CodeGen/RISCV/atomic-cmpxchg.ll
View File

@ -172,7 +172,7 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) {
; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -209,7 +209,7 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) {
; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -718,7 +718,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) {
; RV32I-NEXT: sb a1, 11(sp)
; RV32I-NEXT: addi a1, sp, 11
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_1
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -755,7 +755,7 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) {
; RV64I-NEXT: sb a1, 7(sp)
; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_1
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -956,7 +956,7 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) {
; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -994,7 +994,7 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) {
; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -1516,7 +1516,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) {
; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_2
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -1554,7 +1554,7 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) {
; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_2
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -1700,7 +1700,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) {
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 2
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -1724,7 +1724,7 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) {
; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -2064,7 +2064,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) {
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: addi a3, zero, 5
; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_4
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -2088,7 +2088,7 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) {
; RV64I-NEXT: sw a1, 4(sp)
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -2173,13 +2173,12 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -2190,13 +2189,12 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
@ -2238,10 +2236,10 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: addi a4, zero, 2
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -2254,10 +2252,10 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: mv a4, a5
; RV32IA-NEXT: addi a4, zero, 2
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
@ -2270,7 +2268,7 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 2
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 2
; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16
@ -2295,13 +2293,12 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -2312,13 +2309,12 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
@ -2357,14 +2353,13 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 3
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -2374,14 +2369,13 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 3
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
@ -2419,13 +2413,12 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -2436,13 +2429,12 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
@ -2481,14 +2473,13 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 4
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -2498,14 +2489,13 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 4
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
@ -2543,13 +2533,12 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a5
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: mv a5, zero
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
@ -2560,13 +2549,12 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a5
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: mv a5, zero
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
@ -2605,14 +2593,13 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: mv a6, a4
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 2
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a6
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -2622,14 +2609,13 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
; RV32IA-NEXT: sw ra, 12(sp)
; RV32IA-NEXT: mv a6, a4
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 2
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a6
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
@ -2670,10 +2656,10 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
; RV32I-NEXT: sw a2, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: mv a1, sp
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: addi a4, zero, 5
; RV32I-NEXT: addi a5, zero, 5
; RV32I-NEXT: call __atomic_compare_exchange_8
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
@ -2686,10 +2672,10 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
; RV32IA-NEXT: sw a2, 4(sp)
; RV32IA-NEXT: sw a1, 0(sp)
; RV32IA-NEXT: mv a1, sp
; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: mv a2, a3
; RV32IA-NEXT: mv a3, a4
; RV32IA-NEXT: mv a4, a5
; RV32IA-NEXT: addi a4, zero, 5
; RV32IA-NEXT: addi a5, zero, 5
; RV32IA-NEXT: call __atomic_compare_exchange_8
; RV32IA-NEXT: lw ra, 12(sp)
; RV32IA-NEXT: addi sp, sp, 16
@ -2702,7 +2688,7 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: addi a3, zero, 5
; RV64I-NEXT: mv a4, a3
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: call __atomic_compare_exchange_8
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16

3436
test/CodeGen/RISCV/atomic-rmw.ll
View File

File diff suppressed because it is too large Load Diff

12
test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
View File

@ -36,12 +36,12 @@ define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-NEXT: lui a0, 264704
; RV32IF-NEXT: sw a0, 0(sp)
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp)
@ -63,12 +63,12 @@ define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fsw ft0, 0(sp)
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp)

20
test/CodeGen/RISCV/calling-conv.ll
View File

@ -83,11 +83,11 @@ define i32 @caller_scalars() nounwind {
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: addi a3, zero, 3
; RV32I-FPELIM-NEXT: addi a4, zero, 4
; RV32I-FPELIM-NEXT: lui a6, 262464
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: lui a6, 262464
; RV32I-FPELIM-NEXT: call callee_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
@ -101,11 +101,11 @@ define i32 @caller_scalars() nounwind {
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: addi a3, zero, 3
; RV32I-WITHFP-NEXT: addi a4, zero, 4
; RV32I-WITHFP-NEXT: lui a6, 262464
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: lui a6, 262464
; RV32I-WITHFP-NEXT: call callee_scalars
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
@ -296,6 +296,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
@ -303,7 +304,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM-NEXT: addi a4, zero, 5
; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7
; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
@ -329,6 +329,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
@ -336,7 +337,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: addi a4, zero, 5
; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7
; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
@ -459,10 +459,10 @@ define i32 @caller_many_scalars() nounwind {
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: addi a5, zero, 5
; RV32I-FPELIM-NEXT: addi a6, zero, 6
; RV32I-FPELIM-NEXT: addi a7, zero, 7
; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: call callee_many_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
@ -481,10 +481,10 @@ define i32 @caller_many_scalars() nounwind {
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: addi a5, zero, 5
; RV32I-WITHFP-NEXT: addi a6, zero, 6
; RV32I-WITHFP-NEXT: addi a7, zero, 7
; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: call callee_many_scalars
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
@ -734,9 +734,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
@ -780,9 +780,9 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4

8
test/CodeGen/RISCV/double-calling-conv.ll
View File

@ -95,8 +95,8 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-NEXT: lw a6, 20(sp)
; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a1, zero, 2
; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: mv a4, zero
; RV32IFD-NEXT: call callee_double_split_reg_stack
; RV32IFD-NEXT: lw ra, 28(sp)
@ -138,12 +138,12 @@ define double @caller_double_stack() nounwind {
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a2, zero, 2
; RV32IFD-NEXT: addi a4, zero, 3
; RV32IFD-NEXT: addi a6, zero, 4
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: addi a2, zero, 2
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: addi a4, zero, 3
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: addi a6, zero, 4
; RV32IFD-NEXT: mv a7, zero
; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp)

8
test/CodeGen/RISCV/imm.ll
View File

@ -142,8 +142,8 @@ define i64 @imm64_2() nounwind {
define i64 @imm64_3() nounwind {
; RV32I-LABEL: imm64_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_3:
@ -157,8 +157,8 @@ define i64 @imm64_3() nounwind {
define i64 @imm64_4() nounwind {
; RV32I-LABEL: imm64_4:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_4:
@ -172,8 +172,8 @@ define i64 @imm64_4() nounwind {
define i64 @imm64_5() nounwind {
; RV32I-LABEL: imm64_5:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_5:
@ -249,7 +249,7 @@ define i64 @imm64_9() nounwind {
; RV32I-LABEL: imm64_9:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, -1
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: ret
;
; RV64I-LABEL: imm64_9:

26
test/CodeGen/RISCV/jumptable.ll
View File

@ -8,31 +8,31 @@ define void @jt(i32 %in, i32* %out) {
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: blt a2, a0, .LBB0_4
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: beq a0, a3, .LBB0_7
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: beq a0, a2, .LBB0_7
; RV32I-NEXT: # %bb.2: # %entry
; RV32I-NEXT: bne a0, a2, .LBB0_9
; RV32I-NEXT: addi a2, zero, 2
; RV32I-NEXT: bne a0, a2, .LBB0_10
; RV32I-NEXT: # %bb.3: # %bb2
; RV32I-NEXT: addi a0, zero, 3
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: ret
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_4: # %entry
; RV32I-NEXT: addi a3, zero, 3
; RV32I-NEXT: beq a0, a3, .LBB0_8
; RV32I-NEXT: addi a2, zero, 3
; RV32I-NEXT: beq a0, a2, .LBB0_8
; RV32I-NEXT: # %bb.5: # %entry
; RV32I-NEXT: addi a2, zero, 4
; RV32I-NEXT: bne a0, a2, .LBB0_9
; RV32I-NEXT: bne a0, a2, .LBB0_10
; RV32I-NEXT: # %bb.6: # %bb4
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: ret
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_7: # %bb1
; RV32I-NEXT: addi a0, zero, 4
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: ret
; RV32I-NEXT: j .LBB0_9
; RV32I-NEXT: .LBB0_8: # %bb3
; RV32I-NEXT: sw a2, 0(a1)
; RV32I-NEXT: addi a0, zero, 2
; RV32I-NEXT: .LBB0_9: # %exit
; RV32I-NEXT: sw a0, 0(a1)
; RV32I-NEXT: .LBB0_10: # %exit
; RV32I-NEXT: ret
entry:
switch i32 %in, label %exit [

79
test/CodeGen/RISCV/remat.ll
View File

@ -36,78 +36,77 @@ define i32 @test() nounwind {
; RV32I-NEXT: sw s9, 8(sp)
; RV32I-NEXT: sw s10, 4(sp)
; RV32I-NEXT: sw s11, 0(sp)
; RV32I-NEXT: lui s3, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s3)
; RV32I-NEXT: lui s9, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s9)
; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader
; RV32I-NEXT: lui s5, %hi(k)
; RV32I-NEXT: lui s6, %hi(j)
; RV32I-NEXT: lui s7, %hi(i)
; RV32I-NEXT: lui s9, %hi(g)
; RV32I-NEXT: lui s10, %hi(f)
; RV32I-NEXT: lui s1, %hi(e)
; RV32I-NEXT: lui s8, %hi(d)
; RV32I-NEXT: addi s11, zero, 32
; RV32I-NEXT: lui s2, %hi(c)
; RV32I-NEXT: lui s4, %hi(b)
; RV32I-NEXT: lui s2, %hi(l)
; RV32I-NEXT: lui s3, %hi(k)
; RV32I-NEXT: lui s4, %hi(j)
; RV32I-NEXT: lui s5, %hi(i)
; RV32I-NEXT: lui s7, %hi(g)
; RV32I-NEXT: lui s8, %hi(f)
; RV32I-NEXT: lui s10, %hi(e)
; RV32I-NEXT: lui s1, %hi(d)
; RV32I-NEXT: lui s11, %hi(c)
; RV32I-NEXT: lui s6, %hi(b)
; RV32I-NEXT: .LBB0_2: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: lui a1, %hi(l)
; RV32I-NEXT: lw a1, %lo(l)(a1)
; RV32I-NEXT: lw a1, %lo(l)(s2)
; RV32I-NEXT: beqz a1, .LBB0_4
; RV32I-NEXT: # %bb.3: # %if.then
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a4, %lo(e)(s1)
; RV32I-NEXT: lw a3, %lo(d)(s8)
; RV32I-NEXT: lw a2, %lo(c)(s2)
; RV32I-NEXT: lw a1, %lo(b)(s4)
; RV32I-NEXT: mv a5, s11
; RV32I-NEXT: lw a4, %lo(e)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a2, %lo(c)(s11)
; RV32I-NEXT: lw a1, %lo(b)(s6)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_4: # %if.end
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a0, %lo(k)(s5)
; RV32I-NEXT: lw a0, %lo(k)(s3)
; RV32I-NEXT: beqz a0, .LBB0_6
; RV32I-NEXT: # %bb.5: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a4, %lo(f)(s10)
; RV32I-NEXT: lw a3, %lo(e)(s1)
; RV32I-NEXT: lw a2, %lo(d)(s8)
; RV32I-NEXT: lw a1, %lo(c)(s2)
; RV32I-NEXT: lw a0, %lo(b)(s4)
; RV32I-NEXT: lw a4, %lo(f)(s8)
; RV32I-NEXT: lw a3, %lo(e)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a1, %lo(c)(s11)
; RV32I-NEXT: lw a0, %lo(b)(s6)
; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_6: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a0, %lo(j)(s6)
; RV32I-NEXT: lw a0, %lo(j)(s4)
; RV32I-NEXT: beqz a0, .LBB0_8
; RV32I-NEXT: # %bb.7: # %if.then7
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a4, %lo(g)(s9)
; RV32I-NEXT: lw a3, %lo(f)(s10)
; RV32I-NEXT: lw a2, %lo(e)(s1)
; RV32I-NEXT: lw a1, %lo(d)(s8)
; RV32I-NEXT: lw a0, %lo(c)(s2)
; RV32I-NEXT: mv a5, s11
; RV32I-NEXT: lw a4, %lo(g)(s7)
; RV32I-NEXT: lw a3, %lo(f)(s8)
; RV32I-NEXT: lw a2, %lo(e)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1)
; RV32I-NEXT: lw a0, %lo(c)(s11)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_8: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s7)
; RV32I-NEXT: lw a0, %lo(i)(s5)
; RV32I-NEXT: beqz a0, .LBB0_10
; RV32I-NEXT: # %bb.9: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lui a0, %hi(h)
; RV32I-NEXT: lw a4, %lo(h)(a0)
; RV32I-NEXT: lw a3, %lo(g)(s9)
; RV32I-NEXT: lw a2, %lo(f)(s10)
; RV32I-NEXT: lw a1, %lo(e)(s1)
; RV32I-NEXT: lw a0, %lo(d)(s8)
; RV32I-NEXT: mv a5, s11
; RV32I-NEXT: lw a3, %lo(g)(s7)
; RV32I-NEXT: lw a2, %lo(f)(s8)
; RV32I-NEXT: lw a1, %lo(e)(s10)
; RV32I-NEXT: lw a0, %lo(d)(s1)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: .LBB0_10: # %for.inc
; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1
; RV32I-NEXT: lw a0, %lo(a)(s3)
; RV32I-NEXT: lw a0, %lo(a)(s9)
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: sw a0, %lo(a)(s3)
; RV32I-NEXT: sw a0, %lo(a)(s9)
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1

20
test/CodeGen/RISCV/vararg.ll
View File

@ -185,9 +185,9 @@ define void @va1_caller() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: addi a4, zero, 2
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: call va1
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
@ -199,9 +199,9 @@ define void @va1_caller() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: addi a4, zero, 2
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: call va1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
@ -335,8 +335,8 @@ define void @va2_caller() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: mv a2, zero
; RV32I-FPELIM-NEXT: lui a3, 261888
; RV32I-FPELIM-NEXT: call va2
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
@ -348,8 +348,8 @@ define void @va2_caller() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: mv a2, zero
; RV32I-WITHFP-NEXT: lui a3, 261888
; RV32I-WITHFP-NEXT: call va2
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
@ -498,10 +498,10 @@ define void @va3_caller() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 2
; RV32I-FPELIM-NEXT: lui a2, 261888
; RV32I-FPELIM-NEXT: lui a5, 262144
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: lui a2, 261888
; RV32I-FPELIM-NEXT: mv a4, zero
; RV32I-FPELIM-NEXT: lui a5, 262144
; RV32I-FPELIM-NEXT: call va3
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
@ -514,10 +514,10 @@ define void @va3_caller() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 2
; RV32I-WITHFP-NEXT: lui a2, 261888
; RV32I-WITHFP-NEXT: lui a5, 262144
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: lui a2, 261888
; RV32I-WITHFP-NEXT: mv a4, zero
; RV32I-WITHFP-NEXT: lui a5, 262144
; RV32I-WITHFP-NEXT: call va3
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
@ -707,9 +707,9 @@ define void @va5_aligned_stack_caller() nounwind {
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a6, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a7, zero, 4
@ -752,9 +752,9 @@ define void @va5_aligned_stack_caller() nounwind {
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a6, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a7, zero, 4