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[X86][MMX] Pull out common MMX VT test. NFCI.

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llvm-svn: 322195
This commit is contained in:
Simon Pilgrim 2018-01-10 15:32:19 +00:00
parent c65f288c5c
commit 0166d0b510
1 changed files with 25 additions and 26 deletions
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51
lib/Target/X86/X86ISelLowering.cpp
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@ -30401,34 +30401,33 @@ static SDValue combineBitcast(SDNode *N, SelectionDAG &DAG,
// Since MMX types are special and don't usually play with other vector types, // Since MMX types are special and don't usually play with other vector types,
// it's better to handle them early to be sure we emit efficient code by // it's better to handle them early to be sure we emit efficient code by
// avoiding store-load conversions. // avoiding store-load conversions.
if (VT == MVT::x86mmx) {
// Detect bitcasts between i32 to x86mmx low word.
if (N0.getOpcode() == ISD::BUILD_VECTOR && SrcVT == MVT::v2i32 &&
isNullConstant(N0.getOperand(1))) {
SDValue N00 = N0.getOperand(0);
if (N00.getValueType() == MVT::i32)
return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
}
// Detect bitcasts between i32 to x86mmx low word. // Detect bitcasts between element or subvector extraction to x86mmx.
if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR && if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
SrcVT == MVT::v2i32 && isNullConstant(N0.getOperand(1))) { N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) &&
SDValue N00 = N0->getOperand(0); isNullConstant(N0.getOperand(1))) {
if (N00.getValueType() == MVT::i32) SDValue N00 = N0.getOperand(0);
return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00); if (N00.getValueType().is128BitVector())
} return DAG.getNode(X86ISD::MOVDQ2Q, SDLoc(N00), VT,
DAG.getBitcast(MVT::v2i64, N00));
}
// Detect bitcasts between element or subvector extraction to x86mmx. // Detect bitcasts from FP_TO_SINT to x86mmx.
if (VT == MVT::x86mmx && if (SrcVT == MVT::v2i32 && N0.getOpcode() == ISD::FP_TO_SINT) {
(N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT || SDLoc DL(N0);
N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) && SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
isNullConstant(N0.getOperand(1))) { DAG.getUNDEF(MVT::v2i32));
SDValue N00 = N0->getOperand(0); return DAG.getNode(X86ISD::MOVDQ2Q, DL, VT,
if (N00.getValueType().is128BitVector()) DAG.getBitcast(MVT::v2i64, Res));
return DAG.getNode(X86ISD::MOVDQ2Q, SDLoc(N00), VT, }
DAG.getBitcast(MVT::v2i64, N00));
}
// Detect bitcasts from FP_TO_SINT to x86mmx.
if (VT == MVT::x86mmx && SrcVT == MVT::v2i32 &&
N0.getOpcode() == ISD::FP_TO_SINT) {
SDLoc DL(N0);
SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
DAG.getUNDEF(MVT::v2i32));
return DAG.getNode(X86ISD::MOVDQ2Q, DL, VT,
DAG.getBitcast(MVT::v2i64, Res));
} }
// Convert a bitcasted integer logic operation that has one bitcasted // Convert a bitcasted integer logic operation that has one bitcasted