Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

llvm-svn: 134281
2024-11-22 18:54:02 +01:00 · 2011-07-01 22:36:09 +00:00 · 2011-07-01 22:36:09 +00:00 · 018b2055fc
commit 018b2055fc
parent a230202d5e
54 changed files with 57 additions and 60 deletions
--- a/Makefile.rules
+++ b/Makefile.rules
@ -1775,8 +1775,8 @@ $(ObjDir)/%GenFastISel.inc.tmp : %.td $(ObjDir)/.dir
 	$(Echo) "Building $(<F) \"fast\" instruction selector implementation with tblgen"
 	$(Verb) $(TableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<

-$(TARGET:%=$(ObjDir)/%GenSubtarget.inc.tmp): \
-$(ObjDir)/%GenSubtarget.inc.tmp : %.td $(ObjDir)/.dir
+$(TARGET:%=$(ObjDir)/%GenSubtargetInfo.inc.tmp): \
+$(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir
 	$(Echo) "Building $(<F) subtarget information with tblgen"
 	$(Verb) $(TableGen) -gen-subtarget -o $(call SYSPATH, $@) $<

--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@ -21,7 +21,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "ARMGenSubtarget.inc"
+#include "ARMGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@ -20,7 +20,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "ARMGenSubtarget.inc"
+#include "ARMGenSubtargetInfo.inc"

 namespace llvm {
 class GlobalValue;
--- a/lib/Target/ARM/CMakeLists.txt
+++ b/lib/Target/ARM/CMakeLists.txt
@ -9,7 +9,7 @@ tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(ARMGenDAGISel.inc -gen-dag-isel)
 tablegen(ARMGenFastISel.inc -gen-fast-isel)
 tablegen(ARMGenCallingConv.inc -gen-callingconv)
-tablegen(ARMGenSubtarget.inc -gen-subtarget)
+tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
 tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
 tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)

--- a/lib/Target/ARM/Makefile
+++ b/lib/Target/ARM/Makefile
@ -14,7 +14,7 @@ TARGET = ARM
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
 		ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
-                ARMGenDAGISel.inc ARMGenSubtarget.inc \
+                ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \
                ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
                ARMGenDecoderTables.inc ARMGenEDInfo.inc \
                ARMGenFastISel.inc ARMGenMCCodeEmitter.inc
--- a/lib/Target/Alpha/AlphaSubtarget.cpp
+++ b/lib/Target/Alpha/AlphaSubtarget.cpp
@ -13,12 +13,11 @@

 #include "AlphaSubtarget.h"
 #include "Alpha.h"
-#include "AlphaGenSubtarget.inc"

 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "AlphaGenSubtarget.inc"
+#include "AlphaGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/Alpha/AlphaSubtarget.h
+++ b/lib/Target/Alpha/AlphaSubtarget.h
@ -19,7 +19,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "AlphaGenSubtarget.inc"
+#include "AlphaGenSubtargetInfo.inc"

 namespace llvm {

--- a/lib/Target/Alpha/CMakeLists.txt
+++ b/lib/Target/Alpha/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
 tablegen(AlphaGenCallingConv.inc -gen-callingconv)
-tablegen(AlphaGenSubtarget.inc -gen-subtarget)
+tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(AlphaCodeGen
  AlphaAsmPrinter.cpp
--- a/lib/Target/Alpha/Makefile
+++ b/lib/Target/Alpha/Makefile
@ -14,7 +14,7 @@ TARGET = Alpha
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
                AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
-                AlphaGenCallingConv.inc AlphaGenSubtarget.inc
+                AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc

 DIRS = TargetInfo

--- a/lib/Target/Blackfin/BlackfinSubtarget.cpp
+++ b/lib/Target/Blackfin/BlackfinSubtarget.cpp
@ -16,7 +16,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "BlackfinGenSubtarget.inc"
+#include "BlackfinGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/Blackfin/BlackfinSubtarget.h
+++ b/lib/Target/Blackfin/BlackfinSubtarget.h
@ -18,7 +18,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "BlackfinGenSubtarget.inc"
+#include "BlackfinGenSubtargetInfo.inc"

 namespace llvm {

--- a/lib/Target/Blackfin/CMakeLists.txt
+++ b/lib/Target/Blackfin/CMakeLists.txt
@ -4,7 +4,7 @@ tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
 tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
 tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
-tablegen(BlackfinGenSubtarget.inc -gen-subtarget)
+tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
 tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
 tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)

--- a/lib/Target/Blackfin/Makefile
+++ b/lib/Target/Blackfin/Makefile
@ -14,7 +14,7 @@ TARGET = Blackfin
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
 		BlackfinGenAsmWriter.inc \
-                BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
+                BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \
 		BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc

 DIRS = TargetInfo
--- a/lib/Target/CellSPU/CMakeLists.txt
+++ b/lib/Target/CellSPU/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(SPUGenCodeEmitter.inc -gen-emitter)
 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
 tablegen(SPUGenInstrInfo.inc -gen-instr-info)
 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
-tablegen(SPUGenSubtarget.inc -gen-subtarget)
+tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
 tablegen(SPUGenCallingConv.inc -gen-callingconv)

 add_llvm_target(CellSPUCodeGen
--- a/lib/Target/CellSPU/Makefile
+++ b/lib/Target/CellSPU/Makefile
@ -13,7 +13,7 @@ TARGET = SPU
 BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
 		SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
 		SPUGenDAGISel.inc \
-		SPUGenSubtarget.inc SPUGenCallingConv.inc
+		SPUGenSubtargetInfo.inc SPUGenCallingConv.inc

 DIRS = TargetInfo

--- a/lib/Target/CellSPU/SPUSubtarget.cpp
+++ b/lib/Target/CellSPU/SPUSubtarget.cpp
@ -19,7 +19,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "SPUGenSubtarget.inc"
+#include "SPUGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/CellSPU/SPUSubtarget.h
+++ b/lib/Target/CellSPU/SPUSubtarget.h
@ -19,7 +19,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "SPUGenSubtarget.inc"
+#include "SPUGenSubtargetInfo.inc"

 namespace llvm {
  class GlobalValue;
--- a/lib/Target/MBlaze/CMakeLists.txt
+++ b/lib/Target/MBlaze/CMakeLists.txt
@ -7,7 +7,7 @@ tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
 tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
 tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
-tablegen(MBlazeGenSubtarget.inc -gen-subtarget)
+tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
 tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
 tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)

--- a/lib/Target/MBlaze/MBlazeSubtarget.cpp
+++ b/lib/Target/MBlaze/MBlazeSubtarget.cpp
@ -19,7 +19,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "MBlazeGenSubtarget.inc"
+#include "MBlazeGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/MBlaze/MBlazeSubtarget.h
+++ b/lib/Target/MBlaze/MBlazeSubtarget.h
@ -19,7 +19,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "MBlazeGenSubtarget.inc"
+#include "MBlazeGenSubtargetInfo.inc"

 namespace llvm {

--- a/lib/Target/MBlaze/Makefile
+++ b/lib/Target/MBlaze/Makefile
@ -15,7 +15,7 @@ BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrInfo.inc \
 		MBlazeGenAsmWriter.inc \
                MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
                MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
-                MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+                MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \
                MBlazeGenEDInfo.inc

 DIRS = InstPrinter AsmParser Disassembler TargetInfo
--- a/lib/Target/MSP430/CMakeLists.txt
+++ b/lib/Target/MSP430/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
 tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
 tablegen(MSP430GenCallingConv.inc -gen-callingconv)
-tablegen(MSP430GenSubtarget.inc -gen-subtarget)
+tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(MSP430CodeGen
  MSP430BranchSelector.cpp
--- a/lib/Target/MSP430/MSP430Subtarget.cpp
+++ b/lib/Target/MSP430/MSP430Subtarget.cpp
@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "MSP430GenSubtarget.inc"
+#include "MSP430GenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/MSP430/MSP430Subtarget.h
+++ b/lib/Target/MSP430/MSP430Subtarget.h
@ -17,7 +17,7 @@
 #include "llvm/Target/TargetSubtargetInfo.h"

 #define GET_SUBTARGETINFO_HEADER
-#include "MSP430GenSubtarget.inc"
+#include "MSP430GenSubtargetInfo.inc"

 #include <string>

--- a/lib/Target/MSP430/Makefile
+++ b/lib/Target/MSP430/Makefile
@ -15,7 +15,7 @@ TARGET = MSP430
 BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
 		MSP430GenAsmWriter.inc \
 		MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
-		MSP430GenSubtarget.inc
+		MSP430GenSubtargetInfo.inc

 DIRS = InstPrinter TargetInfo

--- a/lib/Target/Mips/CMakeLists.txt
+++ b/lib/Target/Mips/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(MipsGenInstrInfo.inc -gen-instr-info)
 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
 tablegen(MipsGenDAGISel.inc -gen-dag-isel)
 tablegen(MipsGenCallingConv.inc -gen-callingconv)
-tablegen(MipsGenSubtarget.inc -gen-subtarget)
+tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(MipsCodeGen
  MipsAsmPrinter.cpp
--- a/lib/Target/Mips/Makefile
+++ b/lib/Target/Mips/Makefile
@ -15,7 +15,7 @@ TARGET = Mips
 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
 		MipsGenAsmWriter.inc \
                MipsGenDAGISel.inc MipsGenCallingConv.inc \
-                MipsGenSubtarget.inc
+                MipsGenSubtargetInfo.inc

 DIRS = TargetInfo

--- a/lib/Target/Mips/MipsSubtarget.cpp
+++ b/lib/Target/Mips/MipsSubtarget.cpp
@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "MipsGenSubtarget.inc"
+#include "MipsGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@ -19,7 +19,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "MipsGenSubtarget.inc"
+#include "MipsGenSubtargetInfo.inc"

 namespace llvm {

--- a/lib/Target/PTX/CMakeLists.txt
+++ b/lib/Target/PTX/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv)
 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
 tablegen(PTXGenInstrInfo.inc -gen-instr-info)
 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
-tablegen(PTXGenSubtarget.inc -gen-subtarget)
+tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(PTXCodeGen
  PTXAsmPrinter.cpp
--- a/lib/Target/PTX/Makefile
+++ b/lib/Target/PTX/Makefile
@ -17,7 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
 		PTXGenDAGISel.inc \
 		PTXGenInstrInfo.inc \
 		PTXGenRegisterInfo.inc \
-		PTXGenSubtarget.inc
+		PTXGenSubtargetInfo.inc

 DIRS = TargetInfo

--- a/lib/Target/PTX/PTXSubtarget.cpp
+++ b/lib/Target/PTX/PTXSubtarget.cpp
@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "PTXGenSubtarget.inc"
+#include "PTXGenSubtargetInfo.inc"

 using namespace llvm;

@ -63,5 +63,3 @@ std::string PTXSubtarget::getPTXVersionString() const {
    case PTX_VERSION_2_3: return "2.3";
  }
 }
-
-#include "PTXGenSubtarget.inc"
--- a/lib/Target/PTX/PTXSubtarget.h
+++ b/lib/Target/PTX/PTXSubtarget.h
@ -17,7 +17,7 @@
 #include "llvm/Target/TargetSubtargetInfo.h"

 #define GET_SUBTARGETINFO_HEADER
-#include "PTXGenSubtarget.inc"
+#include "PTXGenSubtargetInfo.inc"

 namespace llvm {
  class PTXSubtarget : public PTXGenSubtargetInfo {
--- a/lib/Target/PowerPC/CMakeLists.txt
+++ b/lib/Target/PowerPC/CMakeLists.txt
@ -7,7 +7,7 @@ tablegen(PPCGenRegisterInfo.inc -gen-register-info)
 tablegen(PPCGenInstrInfo.inc -gen-instr-info)
 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
 tablegen(PPCGenCallingConv.inc -gen-callingconv)
-tablegen(PPCGenSubtarget.inc -gen-subtarget)
+tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(PowerPCCodeGen
  PPCAsmBackend.cpp
--- a/lib/Target/PowerPC/Makefile
+++ b/lib/Target/PowerPC/Makefile
@ -15,7 +15,7 @@ TARGET = PPC
 BUILT_SOURCES = PPCGenRegisterInfo.inc \
                PPCGenAsmWriter.inc  PPCGenCodeEmitter.inc \
                PPCGenInstrInfo.inc PPCGenDAGISel.inc \
-                PPCGenSubtarget.inc PPCGenCallingConv.inc \
+                PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \
                PPCGenMCCodeEmitter.inc

 DIRS = InstPrinter TargetInfo
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@ -20,7 +20,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "PPCGenSubtarget.inc"
+#include "PPCGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/PowerPC/PPCSubtarget.h
+++ b/lib/Target/PowerPC/PPCSubtarget.h
@ -20,7 +20,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "PPCGenSubtarget.inc"
+#include "PPCGenSubtargetInfo.inc"

 // GCC #defines PPC on Linux but we use it as our namespace name
 #undef PPC
--- a/lib/Target/Sparc/CMakeLists.txt
+++ b/lib/Target/Sparc/CMakeLists.txt
@ -4,7 +4,7 @@ tablegen(SparcGenRegisterInfo.inc -gen-register-info)
 tablegen(SparcGenInstrInfo.inc -gen-instr-info)
 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
 tablegen(SparcGenDAGISel.inc -gen-dag-isel)
-tablegen(SparcGenSubtarget.inc -gen-subtarget)
+tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
 tablegen(SparcGenCallingConv.inc -gen-callingconv)

 add_llvm_target(SparcCodeGen
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@ -13,8 +13,8 @@ TARGET = Sparc

 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
-		SparcGenAsmWriter.inc \
-                SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
+		SparcGenAsmWriter.inc SparcGenDAGISel.inc \
+		SparcGenSubtargetInfo.inc SparcGenCallingConv.inc

 DIRS = TargetInfo

--- a/lib/Target/Sparc/SparcSubtarget.cpp
+++ b/lib/Target/Sparc/SparcSubtarget.cpp
@ -16,7 +16,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "SparcGenSubtarget.inc"
+#include "SparcGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/Sparc/SparcSubtarget.h
+++ b/lib/Target/Sparc/SparcSubtarget.h
@ -18,7 +18,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "SparcGenSubtarget.inc"
+#include "SparcGenSubtargetInfo.inc"

 namespace llvm {

--- a/lib/Target/SystemZ/CMakeLists.txt
+++ b/lib/Target/SystemZ/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
 tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
 tablegen(SystemZGenCallingConv.inc -gen-callingconv)
-tablegen(SystemZGenSubtarget.inc -gen-subtarget)
+tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(SystemZCodeGen
  SystemZAsmPrinter.cpp
--- a/lib/Target/SystemZ/Makefile
+++ b/lib/Target/SystemZ/Makefile
@ -13,8 +13,8 @@ TARGET = SystemZ

 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \
-		SystemZGenAsmWriter.inc \
-                SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
+		SystemZGenAsmWriter.inc SystemZGenDAGISel.inc \
+		SystemZGenSubtargetInfo.inc SystemZGenCallingConv.inc

 DIRS = TargetInfo

--- a/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ b/lib/Target/SystemZ/SystemZSubtarget.cpp
@ -19,7 +19,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "SystemZGenSubtarget.inc"
+#include "SystemZGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/SystemZ/SystemZSubtarget.h
+++ b/lib/Target/SystemZ/SystemZSubtarget.h
@ -18,7 +18,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "SystemZGenSubtarget.inc"
+#include "SystemZGenSubtargetInfo.inc"

 namespace llvm {
 class GlobalValue;
--- a/lib/Target/X86/CMakeLists.txt
+++ b/lib/Target/X86/CMakeLists.txt
@ -9,7 +9,7 @@ tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
 tablegen(X86GenDAGISel.inc -gen-dag-isel)
 tablegen(X86GenFastISel.inc -gen-fast-isel)
 tablegen(X86GenCallingConv.inc -gen-callingconv)
-tablegen(X86GenSubtarget.inc -gen-subtarget)
+tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
 tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)

 set(sources
--- a/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
@ -24,7 +24,7 @@
 #include "X86GenInstrInfo.inc"

 #define GET_SUBTARGETINFO_MC_DESC
-#include "X86GenSubtarget.inc"
+#include "X86GenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/X86/Makefile
+++ b/lib/Target/X86/Makefile
@ -16,7 +16,7 @@ BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \
 		X86GenAsmWriter.inc X86GenAsmMatcher.inc \
                X86GenAsmWriter1.inc X86GenDAGISel.inc  \
                X86GenDisassemblerTables.inc X86GenFastISel.inc \
-                X86GenCallingConv.inc X86GenSubtarget.inc \
+                X86GenCallingConv.inc X86GenSubtargetInfo.inc \
 		X86GenEDInfo.inc

 DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc Utils
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@ -24,7 +24,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "X86GenSubtarget.inc"
+#include "X86GenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@ -20,7 +20,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "X86GenSubtarget.inc"
+#include "X86GenSubtargetInfo.inc"

 namespace llvm {
 class GlobalValue;
--- a/lib/Target/XCore/CMakeLists.txt
+++ b/lib/Target/XCore/CMakeLists.txt
@ -5,7 +5,7 @@ tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
 tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
 tablegen(XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(XCoreGenSubtarget.inc -gen-subtarget)
+tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)

 add_llvm_target(XCoreCodeGen
  XCoreAsmPrinter.cpp
--- a/lib/Target/XCore/Makefile
+++ b/lib/Target/XCore/Makefile
@ -15,7 +15,7 @@ TARGET = XCore
 BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \
 		XCoreGenAsmWriter.inc \
                XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
-		XCoreGenSubtarget.inc
+		XCoreGenSubtargetInfo.inc

 DIRS = TargetInfo

--- a/lib/Target/XCore/XCoreSubtarget.cpp
+++ b/lib/Target/XCore/XCoreSubtarget.cpp
@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "XCoreGenSubtarget.inc"
+#include "XCoreGenSubtargetInfo.inc"

 using namespace llvm;

--- a/lib/Target/XCore/XCoreSubtarget.h
+++ b/lib/Target/XCore/XCoreSubtarget.h
@ -19,7 +19,7 @@
 #include <string>

 #define GET_SUBTARGETINFO_HEADER
-#include "XCoreGenSubtarget.inc"
+#include "XCoreGenSubtargetInfo.inc"

 namespace llvm {