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Fix typo. Change %cl to CL in Intel pattern.
llvm-svn: 186815
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@ -537,7 +537,7 @@ def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
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[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
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IIC_SR>;
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def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
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"rol{q}\t{%cl, $dst|$dst, %cl}",
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"rol{q}\t{%cl, $dst|$dst, CL}",
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[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
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IIC_SR>;
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}
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