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[RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
This does not result in changes for any of the current tests, but it might improve debug information in some cases. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D86522
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@ -517,7 +517,7 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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break;
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case RISCV::FSGNJ_D:
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case RISCV::FSGNJ_S:
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// The canonical floatig-point move is fsgnj rd, rs, rs.
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// The canonical floating-point move is fsgnj rd, rs, rs.
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return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
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MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
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case RISCV::ADDI:
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@ -530,6 +530,28 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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return MI.isAsCheapAsAMove();
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}
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Optional<DestSourcePair>
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RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
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if (MI.isMoveReg())
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return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
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switch (MI.getOpcode()) {
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default:
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break;
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case RISCV::ADDI:
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if (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
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return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
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break;
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case RISCV::FSGNJ_D:
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case RISCV::FSGNJ_S:
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// The canonical floating-point move is fsgnj rd, rs, rs.
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if (MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
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MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
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return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
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break;
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}
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return None;
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}
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bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const {
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const MCInstrInfo *MCII = STI.getInstrInfo();
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@ -83,6 +83,9 @@ public:
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bool isAsCheapAsAMove(const MachineInstr &MI) const override;
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Optional<DestSourcePair>
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isCopyInstrImpl(const MachineInstr &MI) const override;
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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