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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00

Change getAllocatableSet() so it returns allocatable registers for a specific register class.

llvm-svn: 36215
This commit is contained in:
Evan Cheng 2007-04-17 20:23:34 +00:00
parent 94e0223e55
commit 023342b277
2 changed files with 11 additions and 6 deletions

View File

@ -241,8 +241,10 @@ public:
}
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not.
BitVector getAllocatableSet(MachineFunction &MF) const;
/// indicating if a register is allocatable or not. If a register class is
/// specified, returns the subset for the class.
BitVector getAllocatableSet(MachineFunction &MF,
const TargetRegisterClass *RC = NULL) const;
const TargetRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&

View File

@ -34,13 +34,16 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
MRegisterInfo::~MRegisterInfo() {}
BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
const TargetRegisterClass *RC) const {
BitVector Allocatable(NumRegs);
for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I;
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
const TargetRegisterClass *TRC = *I;
if (RC && TRC != RC)
continue;
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF),
E = TRC->allocation_order_end(MF); I != E; ++I)
Allocatable.set(*I);
}
return Allocatable;