diff --git a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 58bc7b9bed6..b8be5b05700 100644
--- a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1448,21 +1448,6 @@ bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,
   return false;
 }
 
-bool RISCVDAGToDAGISel::selectRVVUimm5(SDValue N, unsigned Width,
-                                       SDValue &Imm) {
-  if (auto *C = dyn_cast<ConstantSDNode>(N)) {
-    int64_t ImmVal = C->getSExtValue();
-
-    if (!isUInt<5>(ImmVal))
-      return false;
-
-    Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT());
-    return true;
-  }
-
-  return false;
-}
-
 // Merge an ADDI into the offset of a load/store instruction where possible.
 // (load (addi base, off1), off2) -> (load base, off1+off2)
 // (store val, (addi base, off1), off2) -> (store val, base, off1+off2)
diff --git a/lib/Target/RISCV/RISCVISelDAGToDAG.h b/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 7336bd82a0b..8ade57df6c3 100644
--- a/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -74,11 +74,6 @@ public:
     return selectRVVSimm5(N, Width, Imm);
   }
 
-  bool selectRVVUimm5(SDValue N, unsigned Width, SDValue &Imm);
-  template <unsigned Width> bool selectRVVUimm5(SDValue N, SDValue &Imm) {
-    return selectRVVUimm5(N, Width, Imm);
-  }
-
   void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
                                   const SDLoc &DL, unsigned CurOp,
                                   bool IsMasked, bool IsStridedOrIndexed,
diff --git a/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 160b6e3859a..4ae46a18a6f 100644
--- a/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -233,11 +233,6 @@ def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
 def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;
 def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;
 
-def sew8uimm5  : ComplexPattern<XLenVT, 1, "selectRVVUimm5<8>",  []>;
-def sew16uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<16>", []>;
-def sew32uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<32>", []>;
-def sew64uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<64>", []>;
-
 multiclass VPatBinaryVL_VV<SDNode vop,
                            string instruction_name,
                            ValueType result_type,