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https://github.com/RPCS3/llvm-mirror.git
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Prune two MachineInstr.h includes, fix up deps
MachineInstr.h included AliasAnalysis.h, which includes a world of IR constructs mostly unneeded in CodeGen. Prune it. Same for DebugInfoMetadata.h. Noticed with -ftime-trace. llvm-svn: 375311
This commit is contained in:
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8e7a1a8142
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02a07ff3cc
@ -144,7 +144,7 @@ class VLIWPacketizerList {
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protected:
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protected:
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MachineFunction &MF;
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MachineFunction &MF;
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const TargetInstrInfo *TII;
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const TargetInstrInfo *TII;
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AliasAnalysis *AA;
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AAResults *AA;
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// The VLIW Scheduler.
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// The VLIW Scheduler.
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DefaultVLIWScheduler *VLIWScheduler;
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DefaultVLIWScheduler *VLIWScheduler;
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@ -156,9 +156,9 @@ protected:
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std::map<MachineInstr*, SUnit*> MIToSUnit;
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std::map<MachineInstr*, SUnit*> MIToSUnit;
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public:
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public:
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// The AliasAnalysis parameter can be nullptr.
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// The AAResults parameter can be nullptr.
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VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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AliasAnalysis *AA);
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AAResults *AA);
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virtual ~VLIWPacketizerList();
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virtual ~VLIWPacketizerList();
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@ -20,11 +20,9 @@
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#include "llvm/ADT/ilist.h"
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#include "llvm/ADT/ilist.h"
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#include "llvm/ADT/ilist_node.h"
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#include "llvm/ADT/ilist_node.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrDesc.h"
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@ -38,6 +36,7 @@
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namespace llvm {
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namespace llvm {
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class AAResults;
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template <typename T> class ArrayRef;
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template <typename T> class ArrayRef;
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class DIExpression;
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class DIExpression;
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class DILocalVariable;
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class DILocalVariable;
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@ -1043,9 +1042,7 @@ public:
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/// A DBG_VALUE is an entry value iff its debug expression contains the
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/// A DBG_VALUE is an entry value iff its debug expression contains the
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/// DW_OP_LLVM_entry_value operation.
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/// DW_OP_LLVM_entry_value operation.
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bool isDebugEntryValue() const {
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bool isDebugEntryValue() const;
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return isDebugValue() && getDebugExpression()->isEntryValue();
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}
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/// Return true if the instruction is a debug value which describes a part of
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/// Return true if the instruction is a debug value which describes a part of
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/// a variable as unavailable.
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/// a variable as unavailable.
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@ -1414,7 +1411,7 @@ public:
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/// Return true if it is safe to move this instruction. If
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/// Return true if it is safe to move this instruction. If
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/// SawStore is set to true, it means that there is a store (or call) between
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/// SawStore is set to true, it means that there is a store (or call) between
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/// the instruction's location and its intended destination.
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/// the instruction's location and its intended destination.
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bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
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bool isSafeToMove(AAResults *AA, bool &SawStore) const;
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/// Returns true if this instruction's memory access aliases the memory
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/// Returns true if this instruction's memory access aliases the memory
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/// access of Other.
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/// access of Other.
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@ -1426,7 +1423,7 @@ public:
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/// @param AA Optional alias analysis, used to compare memory operands.
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/// @param AA Optional alias analysis, used to compare memory operands.
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/// @param Other MachineInstr to check aliasing against.
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/// @param Other MachineInstr to check aliasing against.
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/// @param UseTBAA Whether to pass TBAA information to alias analysis.
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/// @param UseTBAA Whether to pass TBAA information to alias analysis.
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bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const;
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bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
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/// Return true if this instruction may have an ordered
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/// Return true if this instruction may have an ordered
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/// or volatile memory reference, or if the information describing the memory
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/// or volatile memory reference, or if the information describing the memory
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@ -1441,7 +1438,7 @@ public:
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/// argument area of a function (if it does not change). If the instruction
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/// argument area of a function (if it does not change). If the instruction
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/// does multiple loads, this returns true only if all of the loads are
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/// does multiple loads, this returns true only if all of the loads are
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/// dereferenceable and invariant.
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/// dereferenceable and invariant.
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bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
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bool isDereferenceableInvariantLoad(AAResults *AA) const;
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/// If the specified instruction is a PHI that always merges together the
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/// If the specified instruction is a PHI that always merges together the
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/// same virtual register, return the register, otherwise return 0.
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/// same virtual register, return the register, otherwise return 0.
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@ -367,17 +367,7 @@ public:
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/// Check if given function is safe for not having callee saved registers.
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/// Check if given function is safe for not having callee saved registers.
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/// This is used when interprocedural register allocation is enabled.
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/// This is used when interprocedural register allocation is enabled.
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static bool isSafeForNoCSROpt(const Function &F) {
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static bool isSafeForNoCSROpt(const Function &F);
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if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
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!F.hasFnAttribute(Attribute::NoRecurse))
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return false;
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// Function should not be optimized as tail call.
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for (const User *U : F.users())
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if (auto CS = ImmutableCallSite(U))
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if (CS.isTailCall())
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return false;
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return true;
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}
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/// Check if the no-CSR optimisation is profitable for the given function.
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/// Check if the no-CSR optimisation is profitable for the given function.
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virtual bool isProfitableForNoCSROpt(const Function &F) const {
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virtual bool isProfitableForNoCSROpt(const Function &F) const {
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@ -39,6 +39,7 @@
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namespace llvm {
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namespace llvm {
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class AAResults;
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class DFAPacketizer;
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class DFAPacketizer;
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class InstrItineraryData;
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class InstrItineraryData;
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class LiveIntervals;
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class LiveIntervals;
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@ -95,7 +96,7 @@ public:
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/// registers so that the instructions result is independent of the place
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/// registers so that the instructions result is independent of the place
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/// in the function.
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/// in the function.
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bool isTriviallyReMaterializable(const MachineInstr &MI,
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bool isTriviallyReMaterializable(const MachineInstr &MI,
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AliasAnalysis *AA = nullptr) const {
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AAResults *AA = nullptr) const {
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return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
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return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
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(MI.getDesc().isRematerializable() &&
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(MI.getDesc().isRematerializable() &&
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(isReallyTriviallyReMaterializable(MI, AA) ||
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(isReallyTriviallyReMaterializable(MI, AA) ||
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@ -111,7 +112,7 @@ protected:
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/// not always available.
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/// not always available.
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/// Requirements must be check as stated in isTriviallyReMaterializable() .
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/// Requirements must be check as stated in isTriviallyReMaterializable() .
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virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AliasAnalysis *AA) const {
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AAResults *AA) const {
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return false;
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return false;
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}
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}
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@ -154,7 +155,7 @@ private:
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/// this function does target-independent tests to determine if the
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/// this function does target-independent tests to determine if the
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/// instruction is really trivially rematerializable.
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/// instruction is really trivially rematerializable.
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bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
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bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
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AliasAnalysis *AA) const;
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AAResults *AA) const;
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public:
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public:
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/// These methods return the opcode of the frame setup/destroy instructions
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/// These methods return the opcode of the frame setup/destroy instructions
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@ -12,6 +12,7 @@
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "registerbank"
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#define DEBUG_TYPE "registerbank"
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@ -21,6 +21,7 @@
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/IR/Metadata.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Compiler.h"
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@ -26,6 +26,7 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallPtrSet.h"
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@ -30,6 +30,7 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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#include <queue>
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#include <queue>
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@ -7,6 +7,7 @@
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "MIRVRegNamerUtils.h"
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#include "MIRVRegNamerUtils.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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using namespace llvm;
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@ -832,6 +832,10 @@ const DIExpression *MachineInstr::getDebugExpression() const {
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return cast<DIExpression>(getOperand(3).getMetadata());
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return cast<DIExpression>(getOperand(3).getMetadata());
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}
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}
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bool MachineInstr::isDebugEntryValue() const {
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return isDebugValue() && getDebugExpression()->isEntryValue();
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}
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const TargetRegisterClass*
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const TargetRegisterClass*
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MachineInstr::getRegClassConstraint(unsigned OpIdx,
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MachineInstr::getRegClassConstraint(unsigned OpIdx,
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const TargetInstrInfo *TII,
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const TargetInstrInfo *TII,
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@ -1164,7 +1168,7 @@ void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
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/// isSafeToMove - Return true if it is safe to move this instruction. If
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/// isSafeToMove - Return true if it is safe to move this instruction. If
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/// SawStore is set to true, it means that there is a store (or call) between
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/// SawStore is set to true, it means that there is a store (or call) between
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/// the instruction's location and its intended destination.
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/// the instruction's location and its intended destination.
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bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
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bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
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// Ignore stuff that we obviously can't move.
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// Ignore stuff that we obviously can't move.
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//
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//
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// Treat volatile loads as stores. This is not strictly necessary for
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// Treat volatile loads as stores. This is not strictly necessary for
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@ -1193,7 +1197,7 @@ bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
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return true;
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return true;
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}
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}
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bool MachineInstr::mayAlias(AliasAnalysis *AA, const MachineInstr &Other,
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bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
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bool UseTBAA) const {
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bool UseTBAA) const {
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const MachineFunction *MF = getMF();
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const MachineFunction *MF = getMF();
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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@ -1311,7 +1315,7 @@ bool MachineInstr::hasOrderedMemoryRef() const {
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/// isDereferenceableInvariantLoad - Return true if this instruction will never
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/// isDereferenceableInvariantLoad - Return true if this instruction will never
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/// trap and is loading from a location whose value is invariant across a run of
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/// trap and is loading from a location whose value is invariant across a run of
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/// this function.
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/// this function.
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bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
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bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
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// If the instruction doesn't load at all, it isn't an invariant load.
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// If the instruction doesn't load at all, it isn't an invariant load.
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if (!mayLoad())
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if (!mayLoad())
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return false;
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return false;
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@ -9,6 +9,7 @@
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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using namespace llvm;
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@ -18,6 +18,7 @@
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallSite.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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@ -120,6 +121,18 @@ unsigned TargetFrameLowering::getStackAlignmentSkew(
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return 0;
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return 0;
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}
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}
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bool TargetFrameLowering::isSafeForNoCSROpt(const Function &F) {
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if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
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!F.hasFnAttribute(Attribute::NoRecurse))
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return false;
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// Function should not be optimized as tail call.
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for (const User *U : F.users())
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if (auto CS = ImmutableCallSite(U))
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if (CS.isTailCall())
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return false;
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return true;
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}
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int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
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int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
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llvm_unreachable("getInitialCFAOffset() not implemented!");
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llvm_unreachable("getInitialCFAOffset() not implemented!");
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}
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}
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@ -127,4 +140,4 @@ int TargetFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
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unsigned TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF)
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unsigned TargetFrameLowering::getInitialCFARegister(const MachineFunction &MF)
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const {
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const {
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llvm_unreachable("getInitialCFARegister() not implemented!");
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llvm_unreachable("getInitialCFARegister() not implemented!");
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}
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}
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCLinkerOptimizationHint.h"
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#include "llvm/MC/MCLinkerOptimizationHint.h"
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#include <cassert>
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#include <cassert>
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@ -173,7 +173,7 @@ public:
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}
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}
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AliasAnalysis *AA) const override;
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AAResults *AA) const override;
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1,
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int64_t &Offset1,
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#include "SIDefines.h"
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#include "SIDefines.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/AMDGPUMetadata.h"
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#include "llvm/Support/AMDGPUMetadata.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/EndianStream.h"
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@ -17,6 +17,7 @@
|
|||||||
#include "llvm/IR/Constant.h"
|
#include "llvm/IR/Constant.h"
|
||||||
#include "llvm/IR/Constants.h"
|
#include "llvm/IR/Constants.h"
|
||||||
#include "llvm/IR/GlobalValue.h"
|
#include "llvm/IR/GlobalValue.h"
|
||||||
|
#include "llvm/IR/GlobalVariable.h"
|
||||||
#include "llvm/IR/Type.h"
|
#include "llvm/IR/Type.h"
|
||||||
#include "llvm/Support/Casting.h"
|
#include "llvm/Support/Casting.h"
|
||||||
#include "llvm/Support/Compiler.h"
|
#include "llvm/Support/Compiler.h"
|
||||||
|
@ -130,7 +130,7 @@ INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
|
|||||||
"Hexagon Packetizer", false, false)
|
"Hexagon Packetizer", false, false)
|
||||||
|
|
||||||
HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF,
|
HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF,
|
||||||
MachineLoopInfo &MLI, AliasAnalysis *AA,
|
MachineLoopInfo &MLI, AAResults *AA,
|
||||||
const MachineBranchProbabilityInfo *MBPI, bool Minimal)
|
const MachineBranchProbabilityInfo *MBPI, bool Minimal)
|
||||||
: VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI),
|
: VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI),
|
||||||
Minimal(Minimal) {
|
Minimal(Minimal) {
|
||||||
|
@ -69,8 +69,7 @@ private:
|
|||||||
|
|
||||||
public:
|
public:
|
||||||
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
|
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
|
||||||
AliasAnalysis *AA,
|
AAResults *AA, const MachineBranchProbabilityInfo *MBPI,
|
||||||
const MachineBranchProbabilityInfo *MBPI,
|
|
||||||
bool Minimal);
|
bool Minimal);
|
||||||
|
|
||||||
// initPacketizerState - initialize some internal flags.
|
// initPacketizerState - initialize some internal flags.
|
||||||
|
@ -16,6 +16,7 @@
|
|||||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||||
#include "llvm/CodeGen/MachineFunction.h"
|
#include "llvm/CodeGen/MachineFunction.h"
|
||||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||||
|
#include "llvm/Support/Debug.h"
|
||||||
|
|
||||||
#include <queue>
|
#include <queue>
|
||||||
|
|
||||||
|
@ -248,7 +248,7 @@ public:
|
|||||||
unsigned isLoadFromStackSlot(const MachineInstr &MI,
|
unsigned isLoadFromStackSlot(const MachineInstr &MI,
|
||||||
int &FrameIndex) const override;
|
int &FrameIndex) const override;
|
||||||
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
|
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
|
||||||
AliasAnalysis *AA) const override;
|
AAResults *AA) const override;
|
||||||
unsigned isStoreToStackSlot(const MachineInstr &MI,
|
unsigned isStoreToStackSlot(const MachineInstr &MI,
|
||||||
int &FrameIndex) const override;
|
int &FrameIndex) const override;
|
||||||
|
|
||||||
|
@ -43,7 +43,7 @@ public:
|
|||||||
const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
|
const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
|
||||||
|
|
||||||
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
|
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
|
||||||
AliasAnalysis *AA) const override;
|
AAResults *AA) const override;
|
||||||
|
|
||||||
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
|
const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
|
||||||
|
@ -206,7 +206,7 @@ public:
|
|||||||
int &FrameIndex) const override;
|
int &FrameIndex) const override;
|
||||||
|
|
||||||
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
|
bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
|
||||||
AliasAnalysis *AA) const override;
|
AAResults *AA) const override;
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SubIdx,
|
unsigned DestReg, unsigned SubIdx,
|
||||||
const MachineInstr &Orig,
|
const MachineInstr &Orig,
|
||||||
|
@ -10,6 +10,7 @@
|
|||||||
|
|
||||||
#include "SnippetRepetitor.h"
|
#include "SnippetRepetitor.h"
|
||||||
#include "Target.h"
|
#include "Target.h"
|
||||||
|
#include "llvm/Analysis/TargetLibraryInfo.h"
|
||||||
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
|
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
|
||||||
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
|
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
|
||||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||||
|
Loading…
Reference in New Issue
Block a user