Implement the sadd_with_overflow intrinsic. This is converted into

"ISD::ADDO". ISD::ADDO is lowered into a target-independent form that does the
addition and then checks if the result is less than one of the operands. (If it
is, then there was an overflow.)

llvm-svn: 59779

include/llvm/CodeGen/SelectionDAGNodes.h

@@ -250,13 +250,13 @@ namespace ISD {
     // values.
     ADDE, SUBE,
 
-    // RESULT, OVERFLOW_FLAG, OUTCHAIN = [SU]ADDO(INCHAIN, LHS, RHS) -
-    // Overflow-aware nodes for arithmetic operations. These nodes take two
-    // operands: the normal lhs and rhs to the add. They produce two results:
-    // the normal result of the add, and a flag indicating whether an overflow
-    // occured. These nodes are generated from the llvm.[su]add.with.overflow
-    // intrinsics. They are lowered by target-dependent code.
-    SADDO, UADDO,
+    // RESULT, OVERFLOW_FLAG, OUTCHAIN = ADDO(INCHAIN, LHS, RHS) -
+    // Overflow-aware node for arithmetic operations. This node takes two
+    // operands: the normal lhs and rhs to the add. It produces two results: the
+    // normal result of the add, and a flag indicating whether an overflow
+    // occured. This node is generated from the llvm.sadd.with.overflow
+    // intrinsic. It is lowered by target-dependent code.
+    ADDO,
 
     // Simple binary floating point operators.
     FADD, FSUB, FMUL, FDIV, FREM,

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -190,6 +190,7 @@ namespace {
     SDValue visitBUILD_VECTOR(SDNode *N);
     SDValue visitCONCAT_VECTORS(SDNode *N);
     SDValue visitVECTOR_SHUFFLE(SDNode *N);
+    SDValue visitADDO(SDNode *N);
 
     SDValue XformToShuffleWithZero(SDNode *N);
     SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
@@ -727,6 +728,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
   case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
   case ISD::CONCAT_VECTORS:     return visitCONCAT_VECTORS(N);
   case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
+  case ISD::ADDO:               return visitADDO(N);
   }
   return SDValue();
 }
@@ -5143,6 +5145,34 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
   return SDValue();
 }
 
+SDValue DAGCombiner::visitADDO(SDNode *N) {
+  SDValue Chain = N->getOperand(2);
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+
+  SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
+  AddToWorkList(Sum.getNode());
+  SDValue Cmp = DAG.getSetCC(MVT::i1, Sum, LHS, ISD::SETLT);
+  AddToWorkList(Cmp.getNode());
+
+  MVT ValueVTs[] = { LHS.getValueType(), MVT::i1, MVT::Other };
+  SDValue Ops[] = { Sum, Cmp, Chain };
+
+  SDValue Merge = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 3),
+                                     &Ops[0], 3);
+  SDNode *MNode = Merge.getNode();
+
+  AddToWorkList(MNode);
+  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(MNode, 0));
+  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(MNode, 1));
+  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), SDValue(MNode, 2));
+
+  // Since the node is now dead, remove it from the graph.
+  removeFromWorkList(N);
+  DAG.DeleteNode(N);
+  return SDValue(N, 0);
+}
+
 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
 /// an AND to a vector_shuffle with the destination vector and a zero vector.
 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -5151,8 +5151,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::CARRY_FALSE:         return "carry_false";
   case ISD::ADDC:        return "addc";
   case ISD::ADDE:        return "adde";
-  case ISD::SADDO:       return "saddo";
-  case ISD::UADDO:       return "uaddo";
+  case ISD::ADDO:        return "addo";
   case ISD::SUBC:        return "subc";
   case ISD::SUBE:        return "sube";
   case ISD::SHL_PARTS:   return "shl_parts";

lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp

@@ -4092,6 +4092,31 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
     return 0;
   }
+
+  case Intrinsic::sadd_with_overflow: {
+    // Convert to "ISD::ADDO" instruction.
+    SDValue Chain = getRoot();
+    SDValue Op1 = getValue(I.getOperand(1));
+    SDValue Op2 = getValue(I.getOperand(2));
+    MVT Ty = Op1.getValueType();
+
+    MVT ValueVTs[] = { Ty, MVT::i1, MVT::Other };
+    SDValue Ops[] = { Op1, Op2, Chain };
+
+    SDValue Result = DAG.getNode(ISD::ADDO, DAG.getVTList(&ValueVTs[0], 3),
+                                 &Ops[0], 3);
+
+    setValue(&I, Result);
+
+    unsigned NumArgRegs = Result.getNode()->getNumValues() - 1;
+    DAG.setRoot(SDValue(Result.getNode(), NumArgRegs));
+    return 0;
+  }
+  case Intrinsic::uadd_with_overflow: {
+    // TODO: Convert to "ISD::ADDC" instruction.
+    return 0;
+  }
+
   case Intrinsic::prefetch: {
     SDValue Ops[4];
     Ops[0] = getRoot();