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[AArch64] Add support for NEON scalar floating-point compare instructions.
llvm-svn: 193691
This commit is contained in:
Chad Rosier
parent
41fc626495
commit
02e430c891
@ -168,28 +168,35 @@ def int_aarch64_neon_vcvtf64_u64 :
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// Scalar Floating-point Reciprocal Exponent
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def int_aarch64_neon_vrecpx : Neon_1Arg_Intrinsic;
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class Neon_ICmp_Intrinsic
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: Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], [IntrNoMem]>;
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class Neon_Cmp_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_anyvector_ty],
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[IntrNoMem]>;
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// Scalar Integer Compare Equal
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def int_aarch64_neon_vceq : Neon_ICmp_Intrinsic;
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// Scalar Compare Equal
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def int_aarch64_neon_vceq : Neon_Cmp_Intrinsic;
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// Scalar Integer Compare Greater-Than or Equal
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def int_aarch64_neon_vcge : Neon_ICmp_Intrinsic;
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def int_aarch64_neon_vchs : Neon_ICmp_Intrinsic;
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// Scalar Compare Greater-Than or Equal
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def int_aarch64_neon_vcge : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_vchs : Neon_Cmp_Intrinsic;
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// Scalar Integer Compare Less-Than or Equal
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def int_aarch64_neon_vclez : Neon_ICmp_Intrinsic;
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// Scalar Compare Less-Than or Equal
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def int_aarch64_neon_vclez : Neon_Cmp_Intrinsic;
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// Scalar Compare Less-Than
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def int_aarch64_neon_vcltz : Neon_ICmp_Intrinsic;
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def int_aarch64_neon_vcltz : Neon_Cmp_Intrinsic;
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// Scalar Compare Greater-Than
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def int_aarch64_neon_vcgt : Neon_ICmp_Intrinsic;
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def int_aarch64_neon_vchi : Neon_ICmp_Intrinsic;
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def int_aarch64_neon_vcgt : Neon_Cmp_Intrinsic;
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def int_aarch64_neon_vchi : Neon_Cmp_Intrinsic;
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// Scalar Compare Bitwise Test Bits
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def int_aarch64_neon_vtstd : Neon_ICmp_Intrinsic;
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def int_aarch64_neon_vtstd : Neon_Cmp_Intrinsic;
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// Scalar Floating-point Absolute Compare Greater Than Or Equal
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def int_aarch64_neon_vcage : Neon_Cmp_Intrinsic;
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// Scalar Floating-point Absolute Compare Greater Than
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def int_aarch64_neon_vcagt : Neon_Cmp_Intrinsic;
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// Scalar Signed Saturating Accumulated of Unsigned Value
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def int_aarch64_neon_vuqadd : Neon_2Arg_Intrinsic;
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@ -3492,12 +3492,15 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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unsigned UseNeonMov = VT.getSizeInBits() >= 64;
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// Note we favor lowering MOVI over MVNI.
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// This has implications on the definition of patterns in TableGen to select
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// BIC immediate instructions but not ORR immediate instructions.
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// If this lowering order is changed, TableGen patterns for BIC immediate and
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// ORR immediate instructions have to be updated.
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if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
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if (UseNeonMov &&
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BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
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if (SplatBitSize <= 64) {
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// First attempt to use vector immediate-form MOVI
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EVT NeonMovVT;
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@ -1980,6 +1980,13 @@ def fpz64 : Operand<f64>,
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let DecoderMethod = "DecodeFPZeroOperand";
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}
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def fpz64movi : Operand<i64>,
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ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
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let ParserMatchClass = fpzero_asmoperand;
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let PrintMethod = "printFPZeroOperand";
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let DecoderMethod = "DecodeFPZeroOperand";
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}
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multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> {
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def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
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(outs), ins, "fcmp\t$Rn, $Rm", [pattern],
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@ -3210,8 +3210,8 @@ multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
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class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
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Instruction INSTD>
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: Pat<(v1i64 (opnode (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
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(INSTD VPR64:$Rn, VPR64:$Rm)>;
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: Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
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Instruction INSTH,
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@ -3231,6 +3231,15 @@ multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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// Scalar Three Different
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multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
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@ -3381,10 +3390,36 @@ class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
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[],
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NoItinerary>;
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multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
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string asmop> {
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def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
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(outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
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!strconcat(asmop, " $Rd, $Rn, $FPImm"),
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[],
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NoItinerary>;
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def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
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(outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
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!strconcat(asmop, " $Rd, $Rn, $FPImm"),
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[],
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NoItinerary>;
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}
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class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
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Instruction INSTD>
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: Pat<(v1i64 (opnode (v1i64 VPR64:$Rn), (v1i64 (bitconvert (v8i8 Neon_immAllZeros))))),
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(INSTD VPR64:$Rn, 0)>;
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: Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
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(v1i64 (bitconvert (v8i8 Neon_immAllZeros))))),
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(INSTD FPR64:$Rn, 0)>;
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multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
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(v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
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(INSTS FPR32:$Rn, fpimm:$FPImm)>;
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def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
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(v1f64 (bitconvert (v8i8 Neon_immAllZeros))))),
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(INSTD FPR64:$Rn, 0)>;
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}
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multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
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Instruction INSTD> {
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@ -3669,6 +3704,58 @@ def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
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def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
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CMLTddi>;
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// Scalar Floating-point Compare
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// Scalar Floating-point Compare Mask Equal
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defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
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FCMEQsss, FCMEQddd>;
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// Scalar Floating-point Compare Mask Equal To Zero
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defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
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FCMEQZssi, FCMEQZddi>;
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// Scalar Floating-point Compare Mask Greater Than Or Equal
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defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
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FCMGEsss, FCMGEddd>;
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// Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
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defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
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FCMGEZssi, FCMGEZddi>;
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// Scalar Floating-point Compare Mask Greather Than
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defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
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FCMGTsss, FCMGTddd>;
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// Scalar Floating-point Compare Mask Greather Than Zero
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defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
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FCMGTZssi, FCMGTZddi>;
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// Scalar Floating-point Compare Mask Less Than Or Equal To Zero
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defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
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FCMLEZssi, FCMLEZddi>;
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// Scalar Floating-point Compare Mask Less Than Zero
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defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
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defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
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FCMLTZssi, FCMLTZddi>;
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// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
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defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
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FACGEsss, FACGEddd>;
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// Scalar Floating-point Absolute Compare Mask Greater Than
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defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
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defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
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FACGTsss, FACGTddd>;
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// Scalar Absolute Value
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defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
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defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
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@ -8,7 +8,7 @@ define i64 @test_vceqd(i64 %a, i64 %b) {
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entry:
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%vceq.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vceq1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64> %vceq.i, <1 x i64> %vceq1.i)
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%vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1i64.v1i64(<1 x i64> %vceq.i, <1 x i64> %vceq1.i)
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%0 = extractelement <1 x i64> %vceq2.i, i32 0
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ret i64 %0
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}
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@ -18,7 +18,7 @@ define i64 @test_vceqzd(i64 %a) {
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vceqz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vceqz1.i = call <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64> %vceqz.i, <1 x i64> zeroinitializer)
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%vceqz1.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1i64.v1i64(<1 x i64> %vceqz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vceqz1.i, i32 0
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ret i64 %0
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}
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@ -29,7 +29,7 @@ define i64 @test_vcged(i64 %a, i64 %b) {
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entry:
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%vcge.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcge1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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ret i64 %0
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}
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@ -39,7 +39,7 @@ define i64 @test_vcgezd(i64 %a) {
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcgez.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgez1.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcgez.i, <1 x i64> zeroinitializer)
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%vcgez1.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64> %vcgez.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcgez1.i, i32 0
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ret i64 %0
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}
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@ -50,7 +50,7 @@ define i64 @test_vcgtd(i64 %a, i64 %b) {
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entry:
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%vcgt.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgt1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%0 = extractelement <1 x i64> %vcgt2.i, i32 0
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ret i64 %0
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}
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@ -60,7 +60,7 @@ define i64 @test_vcgtzd(i64 %a) {
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcgtz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgtz1.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgtz.i, <1 x i64> zeroinitializer)
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%vcgtz1.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64> %vcgtz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcgtz1.i, i32 0
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ret i64 %0
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}
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@ -71,7 +71,7 @@ define i64 @test_vcled(i64 %a, i64 %b) {
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entry:
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%vcgt.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcgt1.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%0 = extractelement <1 x i64> %vcgt2.i, i32 0
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ret i64 %0
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}
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@ -81,7 +81,7 @@ define i64 @test_vclezd(i64 %a) {
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; CHECK: cmle {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vclez.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vclez1.i = call <1 x i64> @llvm.aarch64.neon.vclez(<1 x i64> %vclez.i, <1 x i64> zeroinitializer)
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%vclez1.i = call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1i64.v1i64(<1 x i64> %vclez.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vclez1.i, i32 0
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ret i64 %0
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}
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@ -92,7 +92,7 @@ define i64 @test_vcltd(i64 %a, i64 %b) {
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entry:
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%vcge.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcge1.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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ret i64 %0
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}
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@ -102,7 +102,7 @@ define i64 @test_vcltzd(i64 %a) {
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; CHECK: cmlt {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcltz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcltz1.i = call <1 x i64> @llvm.aarch64.neon.vcltz(<1 x i64> %vcltz.i, <1 x i64> zeroinitializer)
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||||
%vcltz1.i = call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1i64.v1i64(<1 x i64> %vcltz.i, <1 x i64> zeroinitializer)
|
||||
%0 = extractelement <1 x i64> %vcltz1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
@ -113,16 +113,16 @@ define i64 @test_vtstd(i64 %a, i64 %b) {
|
||||
entry:
|
||||
%vtst.i = insertelement <1 x i64> undef, i64 %a, i32 0
|
||||
%vtst1.i = insertelement <1 x i64> undef, i64 %b, i32 0
|
||||
%vtst2.i = call <1 x i64> @llvm.aarch64.neon.vtstd(<1 x i64> %vtst.i, <1 x i64> %vtst1.i)
|
||||
%vtst2.i = call <1 x i64> @llvm.aarch64.neon.vtstd.v1i64.v1i64.v1i64(<1 x i64> %vtst.i, <1 x i64> %vtst1.i)
|
||||
%0 = extractelement <1 x i64> %vtst2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare <1 x i64> @llvm.aarch64.neon.vtstd(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcltz(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vchs(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcge(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vclez(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vchi(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcgt(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vceq(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vtstd.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vchs.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vchi.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
||||
|
||||
316
test/CodeGen/AArch64/neon-scalar-fp-compare.ll
Normal file
316
test/CodeGen/AArch64/neon-scalar-fp-compare.ll
Normal file
@ -0,0 +1,316 @@
|
||||
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
|
||||
|
||||
;; Scalar Floating-point Compare
|
||||
|
||||
define i32 @test_vceqs_f32(float %a, float %b) {
|
||||
; CHECK: test_vceqs_f32
|
||||
; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vceq.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vceq1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vceq2.i = call <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float> %vceq.i, <1 x float> %vceq1.i)
|
||||
%0 = extractelement <1 x i32> %vceq2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vceqd_f64(double %a, double %b) {
|
||||
; CHECK: test_vceqd_f64
|
||||
; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vceq.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vceq1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double> %vceq.i, <1 x double> %vceq1.i)
|
||||
%0 = extractelement <1 x i64> %vceq2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vceqzs_f32(float %a) {
|
||||
; CHECK: test_vceqzs_f32
|
||||
; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vceq.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vceq1.i = call <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float> %vceq.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vceq1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vceqzd_f64(double %a) {
|
||||
; CHECK: test_vceqzd_f64
|
||||
; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vceq.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vceq1.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double> %vceq.i, <1 x double> zeroinitializer)
|
||||
%0 = extractelement <1 x i64> %vceq1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcges_f32(float %a, float %b) {
|
||||
; CHECK: test_vcges_f32
|
||||
; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcge1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcge2.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> %vcge1.i)
|
||||
%0 = extractelement <1 x i32> %vcge2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcged_f64(double %a, double %b) {
|
||||
; CHECK: test_vcged_f64
|
||||
; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcge1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> %vcge1.i)
|
||||
%0 = extractelement <1 x i64> %vcge2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcgezs_f32(float %a) {
|
||||
; CHECK: test_vcgezs_f32
|
||||
; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcge1.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vcge1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcgezd_f64(double %a) {
|
||||
; CHECK: test_vcgezd_f64
|
||||
; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcge1.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> zeroinitializer)
|
||||
%0 = extractelement <1 x i64> %vcge1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcgts_f32(float %a, float %b) {
|
||||
; CHECK: test_vcgts_f32
|
||||
; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcgt1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcgt2.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> %vcgt1.i)
|
||||
%0 = extractelement <1 x i32> %vcgt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcgtd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcgtd_f64
|
||||
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcgt1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> %vcgt1.i)
|
||||
%0 = extractelement <1 x i64> %vcgt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcgtzs_f32(float %a) {
|
||||
; CHECK: test_vcgtzs_f32
|
||||
; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcgt1.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vcgt1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcgtzd_f64(double %a) {
|
||||
; CHECK: test_vcgtzd_f64
|
||||
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcgt1.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> zeroinitializer)
|
||||
%0 = extractelement <1 x i64> %vcgt1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcles_f32(float %a, float %b) {
|
||||
; CHECK: test_vcles_f32
|
||||
; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcge1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcge2.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> %vcge1.i)
|
||||
%0 = extractelement <1 x i32> %vcge2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcled_f64(double %a, double %b) {
|
||||
; CHECK: test_vcled_f64
|
||||
; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcge.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcge1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> %vcge1.i)
|
||||
%0 = extractelement <1 x i64> %vcge2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vclezs_f32(float %a) {
|
||||
; CHECK: test_vclezs_f32
|
||||
; CHECK: fcmle {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcle.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcle1.i = call <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float> %vcle.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vcle1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vclezd_f64(double %a) {
|
||||
; CHECK: test_vclezd_f64
|
||||
; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vcle.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcle1.i = call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f64(<1 x double> %vcle.i, <1 x double> zeroinitializer)
|
||||
%0 = extractelement <1 x i64> %vcle1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vclts_f32(float %a, float %b) {
|
||||
; CHECK: test_vclts_f32
|
||||
; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcgt1.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcgt2.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> %vcgt1.i)
|
||||
%0 = extractelement <1 x i32> %vcgt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcltd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcltd_f64
|
||||
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcgt.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcgt1.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> %vcgt1.i)
|
||||
%0 = extractelement <1 x i64> %vcgt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcltzs_f32(float %a) {
|
||||
; CHECK: test_vcltzs_f32
|
||||
; CHECK: fcmlt {{s[0-9]}}, {{s[0-9]}}, #0.0
|
||||
entry:
|
||||
%vclt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vclt1.i = call <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float> %vclt.i, <1 x float> zeroinitializer)
|
||||
%0 = extractelement <1 x i32> %vclt1.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcltzd_f64(double %a) {
|
||||
; CHECK: test_vcltzd_f64
|
||||
; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0
|
||||
entry:
|
||||
%vclt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vclt1.i = call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f64(<1 x double> %vclt.i, <1 x double> zeroinitializer)
|
||||
%0 = extractelement <1 x i64> %vclt1.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcages_f32(float %a, float %b) {
|
||||
; CHECK: test_vcages_f32
|
||||
; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcage1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcage2.i = call <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float> %vcage.i, <1 x float> %vcage1.i)
|
||||
%0 = extractelement <1 x i32> %vcage2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcaged_f64(double %a, double %b) {
|
||||
; CHECK: test_vcaged_f64
|
||||
; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcage1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcage2.i = call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %vcage.i, <1 x double> %vcage1.i)
|
||||
%0 = extractelement <1 x i64> %vcage2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcagts_f32(float %a, float %b) {
|
||||
; CHECK: test_vcagts_f32
|
||||
; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcagt.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcagt1.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcagt2.i = call <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float> %vcagt.i, <1 x float> %vcagt1.i)
|
||||
%0 = extractelement <1 x i32> %vcagt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcagtd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcagtd_f64
|
||||
; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcagt.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcagt1.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcagt2.i = call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %vcagt.i, <1 x double> %vcagt1.i)
|
||||
%0 = extractelement <1 x i64> %vcagt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcales_f32(float %a, float %b) {
|
||||
; CHECK: test_vcales_f32
|
||||
; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcage1.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcage2.i = call <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float> %vcage.i, <1 x float> %vcage1.i)
|
||||
%0 = extractelement <1 x i32> %vcage2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcaled_f64(double %a, double %b) {
|
||||
; CHECK: test_vcaled_f64
|
||||
; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcage.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcage1.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcage2.i = call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %vcage.i, <1 x double> %vcage1.i)
|
||||
%0 = extractelement <1 x i64> %vcage2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
define i32 @test_vcalts_f32(float %a, float %b) {
|
||||
; CHECK: test_vcalts_f32
|
||||
; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
|
||||
entry:
|
||||
%vcalt.i = insertelement <1 x float> undef, float %b, i32 0
|
||||
%vcalt1.i = insertelement <1 x float> undef, float %a, i32 0
|
||||
%vcalt2.i = call <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float> %vcalt.i, <1 x float> %vcalt1.i)
|
||||
%0 = extractelement <1 x i32> %vcalt2.i, i32 0
|
||||
ret i32 %0
|
||||
}
|
||||
|
||||
define i64 @test_vcaltd_f64(double %a, double %b) {
|
||||
; CHECK: test_vcaltd_f64
|
||||
; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
|
||||
entry:
|
||||
%vcalt.i = insertelement <1 x double> undef, double %b, i32 0
|
||||
%vcalt1.i = insertelement <1 x double> undef, double %a, i32 0
|
||||
%vcalt2.i = call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %vcalt.i, <1 x double> %vcalt1.i)
|
||||
%0 = extractelement <1 x i64> %vcalt2.i, i32 0
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
declare <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
declare <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
|
||||
declare <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
|
||||
@ -4397,6 +4397,146 @@
|
||||
// CHECK-ERROR: cmtst b20, d21, d22
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Equal
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmeq s10, h11, s12
|
||||
fcmeq d20, s21, d22
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmeq s10, h11, s12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmeq d20, s21, d22
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Equal To Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmeq h10, s11, #0.0
|
||||
fcmeq d20, s21, #0.0
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmeq h10, s11, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmeq d20, s21, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greater Than Or Equal
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmge s10, h11, s12
|
||||
fcmge d20, s21, d22
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmge s10, h11, s12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmge d20, s21, d22
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmge h10, s11, #0.0
|
||||
fcmge d20, s21, #0.0
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmge h10, s11, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmge d20, s21, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greather Than
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmgt s10, h11, s12
|
||||
fcmgt d20, s21, d22
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmgt s10, h11, s12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmgt d20, s21, d22
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greather Than Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmgt h10, s11, #0.0
|
||||
fcmgt d20, s21, #0.0
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmgt h10, s11, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmgt d20, s21, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Less Than Or Equal To Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmle h10, s11, #0.0
|
||||
fcmle d20, s21, #0.0
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmle h10, s11, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmle d20, s21, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Less Than
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmlt h10, s11, #0.0
|
||||
fcmlt d20, s21, #0.0
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmlt h10, s11, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: fcmlt d20, s21, #0.0
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
facge s10, h11, s12
|
||||
facge d20, s21, d22
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: facge s10, h11, s12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: facge d20, s21, d22
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Absolute Compare Mask Greater Than
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
facgt s10, h11, s12
|
||||
facgt d20, d21, s22
|
||||
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: facgt s10, h11, s12
|
||||
// CHECK-ERROR: ^
|
||||
// CHECK-ERROR: error: invalid operand for instruction
|
||||
// CHECK-ERROR: facgt d20, d21, s22
|
||||
// CHECK-ERROR: ^
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Signed Saturating Accumulated of Unsigned Value
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
103
test/MC/AArch64/neon-scalar-fp-compare.s
Normal file
103
test/MC/AArch64/neon-scalar-fp-compare.s
Normal file
@ -0,0 +1,103 @@
|
||||
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
|
||||
|
||||
// Check that the assembler can handle the documented syntax for AArch64
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Equal
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmeq s10, s11, s12
|
||||
fcmeq d20, d21, d22
|
||||
|
||||
// CHECK: fcmeq s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x5e]
|
||||
// CHECK: fcmeq d20, d21, d22 // encoding: [0xb4,0xe6,0x76,0x5e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Equal To Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmeq s10, s11, #0.0
|
||||
fcmeq d20, d21, #0.0
|
||||
|
||||
// CHECK: fcmeq s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x5e]
|
||||
// CHECK: fcmeq d20, d21, #0.0 // encoding: [0xb4,0xda,0xe0,0x5e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greater Than Or Equal
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmge s10, s11, s12
|
||||
fcmge d20, d21, d22
|
||||
|
||||
// CHECK: fcmge s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x7e]
|
||||
// CHECK: fcmge d20, d21, d22 // encoding: [0xb4,0xe6,0x76,0x7e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmge s10, s11, #0.0
|
||||
fcmge d20, d21, #0.0
|
||||
|
||||
// CHECK: fcmge s10, s11, #0.0 // encoding: [0x6a,0xc9,0xa0,0x7e]
|
||||
// CHECK: fcmge d20, d21, #0.0 // encoding: [0xb4,0xca,0xe0,0x7e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greather Than
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmgt s10, s11, s12
|
||||
fcmgt d20, d21, d22
|
||||
|
||||
// CHECK: fcmgt s10, s11, s12 // encoding: [0x6a,0xe5,0xac,0x7e]
|
||||
// CHECK: fcmgt d20, d21, d22 // encoding: [0xb4,0xe6,0xf6,0x7e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Greather Than Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmgt s10, s11, #0.0
|
||||
fcmgt d20, d21, #0.0
|
||||
|
||||
// CHECK: fcmgt s10, s11, #0.0 // encoding: [0x6a,0xc9,0xa0,0x5e]
|
||||
// CHECK: fcmgt d20, d21, #0.0 // encoding: [0xb4,0xca,0xe0,0x5e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Less Than Or Equal To Zero
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmle s10, s11, #0.0
|
||||
fcmle d20, d21, #0.0
|
||||
|
||||
// CHECK: fcmle s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x7e]
|
||||
// CHECK: fcmle d20, d21, #0.0 // encoding: [0xb4,0xda,0xe0,0x7e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Compare Mask Less Than
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
fcmlt s10, s11, #0.0
|
||||
fcmlt d20, d21, #0.0
|
||||
|
||||
// CHECK: fcmlt s10, s11, #0.0 // encoding: [0x6a,0xe9,0xa0,0x5e]
|
||||
// CHECK: fcmlt d20, d21, #0.0 // encoding: [0xb4,0xea,0xe0,0x5e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
facge s10, s11, s12
|
||||
facge d20, d21, d22
|
||||
|
||||
// CHECK: facge s10, s11, s12 // encoding: [0x6a,0xed,0x2c,0x7e]
|
||||
// CHECK: facge d20, d21, d22 // encoding: [0xb4,0xee,0x76,0x7e]
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Scalar Floating-point Absolute Compare Mask Greater Than
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
facgt s10, s11, s12
|
||||
facgt d20, d21, d22
|
||||
|
||||
// CHECK: facgt s10, s11, s12 // encoding: [0x6a,0xed,0xac,0x7e]
|
||||
// CHECK: facgt d20, d21, d22 // encoding: [0xb4,0xee,0xf6,0x7e]
|
||||
@ -1600,6 +1600,86 @@
|
||||
# CHECK: cmtst d20, d21, d22
|
||||
0xb4,0x8e,0xf6,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Equal
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmeq s10, s11, s12
|
||||
# CHECK: fcmeq d20, d21, d22
|
||||
0x6a,0xe5,0x2c,0x5e
|
||||
0xb4,0xe6,0x76,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Equal To Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmeq s10, s11, #0.0
|
||||
# CHECK: fcmeq d20, d21, #0.0
|
||||
0x6a,0xd9,0xa0,0x5e
|
||||
0xb4,0xda,0xe0,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Greater Than Or Equal
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmge s10, s11, s12
|
||||
# CHECK: fcmge d20, d21, d22
|
||||
0x6a,0xe5,0x2c,0x7e
|
||||
0xb4,0xe6,0x76,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmge s10, s11, #0.0
|
||||
# CHECK: fcmge d20, d21, #0.0
|
||||
0x6a,0xc9,0xa0,0x7e
|
||||
0xb4,0xca,0xe0,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Greather Than
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmgt s10, s11, s12
|
||||
# CHECK: fcmgt d20, d21, d22
|
||||
0x6a,0xe5,0xac,0x7e
|
||||
0xb4,0xe6,0xf6,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Greather Than Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmgt s10, s11, #0.0
|
||||
# CHECK: fcmgt d20, d21, #0.0
|
||||
0x6a,0xc9,0xa0,0x5e
|
||||
0xb4,0xca,0xe0,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Less Than Or Equal To Zero
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmle s10, s11, #0.0
|
||||
# CHECK: fcmle d20, d21, #0.0
|
||||
0x6a,0xd9,0xa0,0x7e
|
||||
0xb4,0xda,0xe0,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Compare Mask Less Than
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: fcmlt s10, s11, #0.0
|
||||
# CHECK: fcmlt d20, d21, #0.0
|
||||
0x6a,0xe9,0xa0,0x5e
|
||||
0xb4,0xea,0xe0,0x5e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: facge s10, s11, s12
|
||||
# CHECK: facge d20, d21, d22
|
||||
0x6a,0xed,0x2c,0x7e
|
||||
0xb4,0xee,0x76,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Floating-point Absolute Compare Mask Greater Than
|
||||
#----------------------------------------------------------------------
|
||||
# CHECK: facgt s10, s11, s12
|
||||
# CHECK: facgt d20, d21, d22
|
||||
0x6a,0xed,0xac,0x7e
|
||||
0xb4,0xee,0xf6,0x7e
|
||||
|
||||
#----------------------------------------------------------------------
|
||||
# Scalar Absolute Value
|
||||
#----------------------------------------------------------------------
|
||||
|
||||
Loading…
Reference in New Issue
Block a user