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https://github.com/RPCS3/llvm-mirror.git
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Revert r253160.
It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
This commit is contained in:
Igor Breger
parent
d43b8f3050
commit
02e6595c76
@ -1579,42 +1579,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v16f32_ty, llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_movshdup_128 :
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GCCBuiltin<"__builtin_ia32_movshdup128_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_movshdup_256 :
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GCCBuiltin<"__builtin_ia32_movshdup256_mask">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_movshdup_512 :
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GCCBuiltin<"__builtin_ia32_movshdup512_mask">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_movsldup_128 :
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GCCBuiltin<"__builtin_ia32_movsldup128_mask">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_movsldup_256 :
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GCCBuiltin<"__builtin_ia32_movsldup256_mask">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8f32_ty, llvm_v8f32_ty, llvm_i8_ty],
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[IntrNoMem]>;
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def int_x86_avx512_mask_movsldup_512 :
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GCCBuiltin<"__builtin_ia32_movsldup512_mask">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v16f32_ty, llvm_v16f32_ty, llvm_i16_ty],
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[IntrNoMem]>;
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}
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// Vector blend
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@ -16,31 +16,11 @@
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "Utils/X86ShuffleDecode.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static unsigned getVectorRegSize(unsigned RegNo) {
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if (X86MCRegisterClasses[X86::VR512RegClassID].contains(RegNo))
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return 512;
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else if (X86MCRegisterClasses[X86::VR256XRegClassID].contains(RegNo))
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return 256;
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else if (X86MCRegisterClasses[X86::VR128XRegClassID].contains(RegNo))
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return 128;
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llvm_unreachable("Unknown vector reg!");
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return 0;
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}
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static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
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unsigned OperandIndex) {
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unsigned OpReg = MI->getOperand(OperandIndex).getReg();
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return MVT::getVectorVT(ScalarVT,
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getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
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}
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/// \brief Extracts the src/dst types for a given zero extension instruction.
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/// \note While the number of elements in DstVT type correct, the
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/// number in the SrcVT type is expanded to fill the src xmm register and the
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@ -127,30 +107,19 @@ static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
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}
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}
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#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
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case X86::V##Inst##Suffix##src: \
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case X86::V##Inst##Suffix##src##k: \
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case X86::V##Inst##Suffix##src##kz:
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#define CASE_VSHUF_COMMON(Inst, Suffix, src2) \
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case X86::VSHUFF##Inst##Suffix##r##src2##i: \
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case X86::VSHUFF##Inst##Suffix##r##src2##ik: \
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case X86::VSHUFF##Inst##Suffix##r##src2##ikz: \
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case X86::VSHUFI##Inst##Suffix##r##src2##i: \
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case X86::VSHUFI##Inst##Suffix##r##src2##ik: \
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case X86::VSHUFI##Inst##Suffix##r##src2##ikz:
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#define CASE_SSE_INS_COMMON(Inst, src) \
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case X86::Inst##src:
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#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
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case X86::V##Inst##Suffix##src:
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#define CASE_MOVDUP(Inst, src) \
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CASE_MASK_INS_COMMON(Inst, Z, r##src) \
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CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
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CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
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CASE_AVX_INS_COMMON(Inst, , r##src) \
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CASE_AVX_INS_COMMON(Inst, Y, r##src) \
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CASE_SSE_INS_COMMON(Inst, r##src) \
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#define CASE_VSHUF(Inst, src) \
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CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
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CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
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CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
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CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
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#define CASE_VSHUF(Inst) \
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CASE_VSHUF_COMMON(Inst, Z, r) \
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CASE_VSHUF_COMMON(Inst, Z, m) \
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CASE_VSHUF_COMMON(Inst, Z256, r) \
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CASE_VSHUF_COMMON(Inst, Z256, m) \
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/// \brief Extracts the types and if it has memory operand for a given
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/// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
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@ -160,15 +129,25 @@ static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
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default:
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llvm_unreachable("Unknown VSHUF64x2 family instructions.");
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break;
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CASE_VSHUF(64X2, m)
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CASE_VSHUF_COMMON(64X2, Z, m)
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HasMemOp = true; // FALL THROUGH.
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CASE_VSHUF(64X2, r)
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VT = getRegOperandVectorVT(MI, MVT::i64, 0);
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CASE_VSHUF_COMMON(64X2, Z, r)
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VT = MVT::v8i64;
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break;
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CASE_VSHUF(32X4, m)
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CASE_VSHUF_COMMON(64X2, Z256, m)
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HasMemOp = true; // FALL THROUGH.
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CASE_VSHUF(32X4, r)
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VT = getRegOperandVectorVT(MI, MVT::i32, 0);
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CASE_VSHUF_COMMON(64X2, Z256, r)
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VT = MVT::v4i64;
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break;
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CASE_VSHUF_COMMON(32X4, Z, m)
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HasMemOp = true; // FALL THROUGH.
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CASE_VSHUF_COMMON(32X4, Z, r)
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VT = MVT::v16i32;
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break;
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CASE_VSHUF_COMMON(32X4, Z256, m)
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HasMemOp = true; // FALL THROUGH.
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CASE_VSHUF_COMMON(32X4, Z256, r)
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VT = MVT::v8i32;
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break;
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}
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}
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@ -318,24 +297,43 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVHLPSMask(2, ShuffleMask);
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break;
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CASE_MOVDUP(MOVSLDUP, r)
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Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
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case X86::MOVSLDUPrr:
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case X86::VMOVSLDUPrr:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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CASE_MOVDUP(MOVSLDUP, m) {
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MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
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case X86::MOVSLDUPrm:
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case X86::VMOVSLDUPrm:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVSLDUPMask(VT, ShuffleMask);
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DecodeMOVSLDUPMask(MVT::v4f32, ShuffleMask);
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break;
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}
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CASE_MOVDUP(MOVSHDUP, r)
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Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
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case X86::VMOVSHDUPYrr:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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CASE_MOVDUP(MOVSHDUP, m) {
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MVT VT = getRegOperandVectorVT(MI, MVT::f32, 0);
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case X86::VMOVSHDUPYrm:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVSHDUPMask(VT, ShuffleMask);
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DecodeMOVSHDUPMask(MVT::v8f32, ShuffleMask);
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break;
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}
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case X86::VMOVSLDUPYrr:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VMOVSLDUPYrm:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVSLDUPMask(MVT::v8f32, ShuffleMask);
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break;
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case X86::MOVSHDUPrr:
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case X86::VMOVSHDUPrr:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::MOVSHDUPrm:
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case X86::VMOVSHDUPrm:
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVSHDUPMask(MVT::v4f32, ShuffleMask);
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break;
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case X86::VMOVDDUPYrr:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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@ -773,10 +771,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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CASE_VSHUF(64X2, r)
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CASE_VSHUF(64X2, m)
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CASE_VSHUF(32X4, r)
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CASE_VSHUF(32X4, m) {
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CASE_VSHUF(64X2)
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CASE_VSHUF(32X4) {
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MVT VT;
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bool HasMemOp;
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unsigned NumOp = MI->getNumOperands();
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@ -4254,6 +4254,35 @@ defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
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def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
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(VMOVDDUPZrm addr:$src)>;
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//===---------------------------------------------------------------------===//
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// Replicate Single FP - MOVSHDUP and MOVSLDUP
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//===---------------------------------------------------------------------===//
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multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
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ValueType vt, RegisterClass RC, PatFrag mem_frag,
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X86MemOperand x86memop> {
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def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
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let mayLoad = 1 in
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def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
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}
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defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
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v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
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v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
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def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
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(VMOVSHDUPZrm addr:$src)>;
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def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
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def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
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(VMOVSLDUPZrm addr:$src)>;
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//===----------------------------------------------------------------------===//
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// Move Low to High and High to Low packed FP Instructions
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//===----------------------------------------------------------------------===//
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@ -7027,13 +7056,13 @@ defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
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multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _> {
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defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1), OpcodeStr,
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(ins _.RC:$src1), OpcodeStr##_.Suffix,
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"$src1", "$src1",
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(_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
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let mayLoad = 1 in
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defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.MemOp:$src1), OpcodeStr,
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(ins _.MemOp:$src1), OpcodeStr##_.Suffix,
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"$src1", "$src1",
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(_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
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EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
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@ -7044,7 +7073,7 @@ multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
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avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
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let mayLoad = 1 in
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defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.ScalarMemOp:$src1), OpcodeStr,
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(ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
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"${src1}"##_.BroadcastStr,
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"${src1}"##_.BroadcastStr,
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(_.VT (OpNode (X86VBroadcast
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@ -7081,16 +7110,15 @@ multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
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SDNode OpNode, Predicate prd> {
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defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
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defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
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prd>, VEX_W;
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defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
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prd>;
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defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
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}
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multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
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SDNode OpNode, Predicate prd> {
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defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
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defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
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defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
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defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
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}
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multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
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@ -7124,19 +7152,6 @@ multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
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defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
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defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
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//===---------------------------------------------------------------------===//
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// Replicate Single FP - MOVSHDUP and MOVSLDUP
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//===---------------------------------------------------------------------===//
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multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
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defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
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HasAVX512>, XS;
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let isCodeGenOnly = 1 in
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defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
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HasAVX512>, XS;
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}
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defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
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defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - Unpack Instructions
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//===----------------------------------------------------------------------===//
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@ -5135,7 +5135,7 @@ def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
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}
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let Predicates = [HasAVX, NoVLX] in {
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let Predicates = [HasAVX] in {
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defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
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v4f32, VR128, loadv4f32, f128mem>, VEX;
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defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
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@ -5150,7 +5150,7 @@ defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
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defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
|
||||
memopv4f32, f128mem>;
|
||||
|
||||
let Predicates = [HasAVX, NoVLX] in {
|
||||
let Predicates = [HasAVX] in {
|
||||
def : Pat<(v4i32 (X86Movshdup VR128:$src)),
|
||||
(VMOVSHDUPrr VR128:$src)>;
|
||||
def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
|
||||
|
||||
@ -776,10 +776,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FMAX, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMAX,
|
||||
X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FMAX, X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FMAX, X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMAX,
|
||||
X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMAX,
|
||||
X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_pd_128, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_pd_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
|
||||
@ -788,22 +788,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
|
||||
X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FMIN, X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FMIN, X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_movshdup_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::MOVSHDUP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_movshdup_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::MOVSHDUP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_movshdup_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::MOVSHDUP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_movsldup_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::MOVSLDUP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_movsldup_256, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::MOVSLDUP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_movsldup_512, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::MOVSLDUP, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMIN,
|
||||
X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK_RM, X86ISD::FMIN,
|
||||
X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_pd_128, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_pd_256, INTR_TYPE_2OP_MASK, ISD::FMUL, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_pd_512, INTR_TYPE_2OP_MASK, ISD::FMUL,
|
||||
|
||||
@ -344,30 +344,6 @@ define <16 x i16> @shuffle_v16i16_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_0
|
||||
ret <16 x i16> %shuffle
|
||||
}
|
||||
|
||||
define <8 x float> @shuffle_v8f32_11335577(<8 x float> %a, <8 x float> %b) {
|
||||
; vmovshdup 256 test
|
||||
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
|
||||
ret <8 x float> %shuffle
|
||||
}
|
||||
|
||||
define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
|
||||
; vmovshdup 128 test
|
||||
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
ret <4 x float> %shuffle
|
||||
}
|
||||
|
||||
define <8 x float> @shuffle_v8f32_00224466(<8 x float> %a, <8 x float> %b) {
|
||||
; vmovsldup 256 test
|
||||
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
|
||||
ret <8 x float> %shuffle
|
||||
}
|
||||
|
||||
define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) {
|
||||
; vmovsldup 128 test
|
||||
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
ret <4 x float> %shuffle
|
||||
}
|
||||
|
||||
define <2 x double> @insert_mem_lo_v2f64(double* %ptr, <2 x double> %b) {
|
||||
%a = load double, double* %ptr
|
||||
%v = insertelement <2 x double> undef, double %a, i32 0
|
||||
|
||||
@ -4676,49 +4676,3 @@ define <8 x i64>@test_int_x86_avx512_maskz_pternlog_q_512(<8 x i64> %x0, <8 x i6
|
||||
ret <8 x i64> %res2
|
||||
}
|
||||
|
||||
declare <16 x float> @llvm.x86.avx512.mask.movsldup.512(<16 x float>, <16 x float>, i16)
|
||||
|
||||
define <16 x float>@test_int_x86_avx512_mask_movsldup_512(<16 x float> %x0, <16 x float> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vmovsldup %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: ## zmm1 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
|
||||
; CHECK-NEXT: vmovsldup %zmm0, %zmm2 {%k1} {z}
|
||||
; CHECK-NEXT: ## zmm2 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
|
||||
; CHECK-NEXT: vmovsldup %zmm0, %zmm0
|
||||
; CHECK-NEXT: ## zmm0 = zmm0[0,0,2,2,4,4,6,6,8,8,10,10,12,12,14,14]
|
||||
; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: vaddps %zmm0, %zmm2, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.movsldup.512(<16 x float> %x0, <16 x float> %x1, i16 %x2)
|
||||
%res1 = call <16 x float> @llvm.x86.avx512.mask.movsldup.512(<16 x float> %x0, <16 x float> %x1, i16 -1)
|
||||
%res2 = call <16 x float> @llvm.x86.avx512.mask.movsldup.512(<16 x float> %x0, <16 x float> zeroinitializer, i16 %x2)
|
||||
%res3 = fadd <16 x float> %res, %res1
|
||||
%res4 = fadd <16 x float> %res2, %res3
|
||||
ret <16 x float> %res4
|
||||
}
|
||||
|
||||
declare <16 x float> @llvm.x86.avx512.mask.movshdup.512(<16 x float>, <16 x float>, i16)
|
||||
|
||||
define <16 x float>@test_int_x86_avx512_mask_movshdup_512(<16 x float> %x0, <16 x float> %x1, i16 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_512:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: kmovw %edi, %k1
|
||||
; CHECK-NEXT: vmovshdup %zmm0, %zmm1 {%k1}
|
||||
; CHECK-NEXT: ## zmm1 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
|
||||
; CHECK-NEXT: vmovshdup %zmm0, %zmm2 {%k1} {z}
|
||||
; CHECK-NEXT: ## zmm2 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
|
||||
; CHECK-NEXT: vmovshdup %zmm0, %zmm0
|
||||
; CHECK-NEXT: ## zmm0 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
|
||||
; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
|
||||
; CHECK-NEXT: vaddps %zmm0, %zmm2, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <16 x float> @llvm.x86.avx512.mask.movshdup.512(<16 x float> %x0, <16 x float> %x1, i16 %x2)
|
||||
%res1 = call <16 x float> @llvm.x86.avx512.mask.movshdup.512(<16 x float> %x0, <16 x float> %x1, i16 -1)
|
||||
%res2 = call <16 x float> @llvm.x86.avx512.mask.movshdup.512(<16 x float> %x0, <16 x float> zeroinitializer, i16 %x2)
|
||||
%res3 = fadd <16 x float> %res, %res1
|
||||
%res4 = fadd <16 x float> %res2, %res3
|
||||
ret <16 x float> %res4
|
||||
}
|
||||
|
||||
|
||||
@ -5334,100 +5334,3 @@ define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0) {
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float>, i32, <8 x i16>, i8) nounwind readonly
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_movsldup_128(<4 x float> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vmovsldup %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: ## xmm1 = xmm0[0,0,2,2]
|
||||
; CHECK-NEXT: vmovsldup %xmm0, %xmm2 {%k1} {z}
|
||||
; CHECK-NEXT: ## xmm2 = xmm0[0,0,2,2]
|
||||
; CHECK-NEXT: vmovsldup %xmm0, %xmm0
|
||||
; CHECK-NEXT: ## xmm0 = xmm0[0,0,2,2]
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = call <4 x float> @llvm.x86.avx512.mask.movsldup.128(<4 x float> %x0, <4 x float> zeroinitializer, i8 %x2)
|
||||
%res3 = fadd <4 x float> %res, %res1
|
||||
%res4 = fadd <4 x float> %res2, %res3
|
||||
ret <4 x float> %res4
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float>, <8 x float>, i8)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_movsldup_256(<8 x float> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_movsldup_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vmovsldup %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: ## ymm1 = ymm0[0,0,2,2,4,4,6,6]
|
||||
; CHECK-NEXT: vmovsldup %ymm0, %ymm2 {%k1} {z}
|
||||
; CHECK-NEXT: ## ymm2 = ymm0[0,0,2,2,4,4,6,6]
|
||||
; CHECK-NEXT: vmovsldup %ymm0, %ymm0
|
||||
; CHECK-NEXT: ## ymm0 = ymm0[0,0,2,2,4,4,6,6]
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> %x1, i8 %x2)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> %x1, i8 -1)
|
||||
%res2 = call <8 x float> @llvm.x86.avx512.mask.movsldup.256(<8 x float> %x0, <8 x float> zeroinitializer, i8 %x2)
|
||||
%res3 = fadd <8 x float> %res, %res1
|
||||
%res4 = fadd <8 x float> %res2, %res3
|
||||
ret <8 x float> %res4
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float>, <4 x float>, i8)
|
||||
|
||||
define <4 x float>@test_int_x86_avx512_mask_movshdup_128(<4 x float> %x0, <4 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_128:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vmovshdup %xmm0, %xmm1 {%k1}
|
||||
; CHECK-NEXT: ## xmm1 = xmm0[1,1,3,3]
|
||||
; CHECK-NEXT: vmovshdup %xmm0, %xmm2 {%k1} {z}
|
||||
; CHECK-NEXT: ## xmm2 = xmm0[1,1,3,3]
|
||||
; CHECK-NEXT: vmovshdup %xmm0, %xmm0
|
||||
; CHECK-NEXT: ## xmm0 = xmm0[1,1,3,3]
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; CHECK-NEXT: vaddps %xmm0, %xmm2, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> %x1, i8 %x2)
|
||||
%res1 = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> %x1, i8 -1)
|
||||
%res2 = call <4 x float> @llvm.x86.avx512.mask.movshdup.128(<4 x float> %x0, <4 x float> zeroinitializer, i8 %x2)
|
||||
%res3 = fadd <4 x float> %res, %res1
|
||||
%res4 = fadd <4 x float> %res2, %res3
|
||||
ret <4 x float> %res4
|
||||
}
|
||||
|
||||
declare <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float>, <8 x float>, i8)
|
||||
|
||||
define <8 x float>@test_int_x86_avx512_mask_movshdup_256(<8 x float> %x0, <8 x float> %x1, i8 %x2) {
|
||||
; CHECK-LABEL: test_int_x86_avx512_mask_movshdup_256:
|
||||
; CHECK: ## BB#0:
|
||||
; CHECK-NEXT: movzbl %dil, %eax
|
||||
; CHECK-NEXT: kmovw %eax, %k1
|
||||
; CHECK-NEXT: vmovshdup %ymm0, %ymm1 {%k1}
|
||||
; CHECK-NEXT: ## ymm1 = ymm0[1,1,3,3,5,5,7,7]
|
||||
; CHECK-NEXT: vmovshdup %ymm0, %ymm2 {%k1} {z}
|
||||
; CHECK-NEXT: ## ymm2 = ymm0[1,1,3,3,5,5,7,7]
|
||||
; CHECK-NEXT: vmovshdup %ymm0, %ymm0
|
||||
; CHECK-NEXT: ## ymm0 = ymm0[1,1,3,3,5,5,7,7]
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0
|
||||
; CHECK-NEXT: vaddps %ymm0, %ymm2, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
%res = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> %x1, i8 %x2)
|
||||
%res1 = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> %x1, i8 -1)
|
||||
%res2 = call <8 x float> @llvm.x86.avx512.mask.movshdup.256(<8 x float> %x0, <8 x float> zeroinitializer, i8 %x2)
|
||||
%res3 = fadd <8 x float> %res, %res1
|
||||
%res4 = fadd <8 x float> %res2, %res3
|
||||
ret <8 x float> %res4
|
||||
}
|
||||
|
||||
|
||||
@ -18297,78 +18297,6 @@ vpermilpd $0x23, 0x400(%rbx), %zmm2
|
||||
// CHECK: encoding: [0xc5,0xf9,0x7e,0xaa,0xfc,0xfd,0xff,0xff]
|
||||
vmovd %xmm5, -516(%rdx)
|
||||
|
||||
// CHECK: vmovshdup %zmm27, %zmm16
|
||||
// CHECK: encoding: [0x62,0x81,0x7e,0x48,0x16,0xc3]
|
||||
vmovshdup %zmm27, %zmm16
|
||||
|
||||
// CHECK: vmovshdup %zmm27, %zmm16 {%k4}
|
||||
// CHECK: encoding: [0x62,0x81,0x7e,0x4c,0x16,0xc3]
|
||||
vmovshdup %zmm27, %zmm16 {%k4}
|
||||
|
||||
// CHECK: vmovshdup %zmm27, %zmm16 {%k4} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x7e,0xcc,0x16,0xc3]
|
||||
vmovshdup %zmm27, %zmm16 {%k4} {z}
|
||||
|
||||
// CHECK: vmovshdup (%rcx), %zmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x16,0x01]
|
||||
vmovshdup (%rcx), %zmm16
|
||||
|
||||
// CHECK: vmovshdup 291(%rax,%r14,8), %zmm16
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x48,0x16,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovshdup 291(%rax,%r14,8), %zmm16
|
||||
|
||||
// CHECK: vmovshdup 8128(%rdx), %zmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x16,0x42,0x7f]
|
||||
vmovshdup 8128(%rdx), %zmm16
|
||||
|
||||
// CHECK: vmovshdup 8192(%rdx), %zmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x16,0x82,0x00,0x20,0x00,0x00]
|
||||
vmovshdup 8192(%rdx), %zmm16
|
||||
|
||||
// CHECK: vmovshdup -8192(%rdx), %zmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x16,0x42,0x80]
|
||||
vmovshdup -8192(%rdx), %zmm16
|
||||
|
||||
// CHECK: vmovshdup -8256(%rdx), %zmm16
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x48,0x16,0x82,0xc0,0xdf,0xff,0xff]
|
||||
vmovshdup -8256(%rdx), %zmm16
|
||||
|
||||
// CHECK: vmovsldup %zmm14, %zmm13
|
||||
// CHECK: encoding: [0x62,0x51,0x7e,0x48,0x12,0xee]
|
||||
vmovsldup %zmm14, %zmm13
|
||||
|
||||
// CHECK: vmovsldup %zmm14, %zmm13 {%k6}
|
||||
// CHECK: encoding: [0x62,0x51,0x7e,0x4e,0x12,0xee]
|
||||
vmovsldup %zmm14, %zmm13 {%k6}
|
||||
|
||||
// CHECK: vmovsldup %zmm14, %zmm13 {%k6} {z}
|
||||
// CHECK: encoding: [0x62,0x51,0x7e,0xce,0x12,0xee]
|
||||
vmovsldup %zmm14, %zmm13 {%k6} {z}
|
||||
|
||||
// CHECK: vmovsldup (%rcx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7e,0x48,0x12,0x29]
|
||||
vmovsldup (%rcx), %zmm13
|
||||
|
||||
// CHECK: vmovsldup 291(%rax,%r14,8), %zmm13
|
||||
// CHECK: encoding: [0x62,0x31,0x7e,0x48,0x12,0xac,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovsldup 291(%rax,%r14,8), %zmm13
|
||||
|
||||
// CHECK: vmovsldup 8128(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7e,0x48,0x12,0x6a,0x7f]
|
||||
vmovsldup 8128(%rdx), %zmm13
|
||||
|
||||
// CHECK: vmovsldup 8192(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7e,0x48,0x12,0xaa,0x00,0x20,0x00,0x00]
|
||||
vmovsldup 8192(%rdx), %zmm13
|
||||
|
||||
// CHECK: vmovsldup -8192(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7e,0x48,0x12,0x6a,0x80]
|
||||
vmovsldup -8192(%rdx), %zmm13
|
||||
|
||||
// CHECK: vmovsldup -8256(%rdx), %zmm13
|
||||
// CHECK: encoding: [0x62,0x71,0x7e,0x48,0x12,0xaa,0xc0,0xdf,0xff,0xff]
|
||||
vmovsldup -8256(%rdx), %zmm13
|
||||
|
||||
// CHECK: vmovlps (%rcx), %xmm20, %xmm7
|
||||
// CHECK: encoding: [0x62,0xf1,0x5c,0x00,0x12,0x39]
|
||||
vmovlps (%rcx), %xmm20, %xmm7
|
||||
|
||||
@ -21978,148 +21978,3 @@ vaddpd {rz-sae}, %zmm2, %zmm1, %zmm1
|
||||
// CHECK: vcvtps2ph $123, %ymm30, -2064(%rdx)
|
||||
// CHECK: encoding: [0x62,0x63,0x7d,0x28,0x1d,0xb2,0xf0,0xf7,0xff,0xff,0x7b]
|
||||
vcvtps2ph $0x7b, %ymm30, -2064(%rdx)
|
||||
|
||||
// CHECK: vmovshdup %xmm18, %xmm23
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x08,0x16,0xfa]
|
||||
vmovshdup %xmm18, %xmm23
|
||||
|
||||
// CHECK: vmovshdup %xmm18, %xmm23 {%k2}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x0a,0x16,0xfa]
|
||||
vmovshdup %xmm18, %xmm23 {%k2}
|
||||
|
||||
// CHECK: vmovshdup %xmm18, %xmm23 {%k2} {z}
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x8a,0x16,0xfa]
|
||||
vmovshdup %xmm18, %xmm23 {%k2} {z}
|
||||
|
||||
// CHECK: vmovshdup (%rcx), %xmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x08,0x16,0x39]
|
||||
vmovshdup (%rcx), %xmm23
|
||||
|
||||
// CHECK: vmovshdup 291(%rax,%r14,8), %xmm23
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x08,0x16,0xbc,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovshdup 291(%rax,%r14,8), %xmm23
|
||||
|
||||
// CHECK: vmovshdup 2032(%rdx), %xmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x08,0x16,0x7a,0x7f]
|
||||
vmovshdup 2032(%rdx), %xmm23
|
||||
|
||||
// CHECK: vmovshdup 2048(%rdx), %xmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x08,0x16,0xba,0x00,0x08,0x00,0x00]
|
||||
vmovshdup 2048(%rdx), %xmm23
|
||||
|
||||
// CHECK: vmovshdup -2048(%rdx), %xmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x08,0x16,0x7a,0x80]
|
||||
vmovshdup -2048(%rdx), %xmm23
|
||||
|
||||
// CHECK: vmovshdup -2064(%rdx), %xmm23
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x08,0x16,0xba,0xf0,0xf7,0xff,0xff]
|
||||
vmovshdup -2064(%rdx), %xmm23
|
||||
|
||||
// CHECK: vmovshdup %ymm24, %ymm18
|
||||
// CHECK: encoding: [0x62,0x81,0x7e,0x28,0x16,0xd0]
|
||||
vmovshdup %ymm24, %ymm18
|
||||
|
||||
// CHECK: vmovshdup %ymm24, %ymm18 {%k3}
|
||||
// CHECK: encoding: [0x62,0x81,0x7e,0x2b,0x16,0xd0]
|
||||
vmovshdup %ymm24, %ymm18 {%k3}
|
||||
|
||||
// CHECK: vmovshdup %ymm24, %ymm18 {%k3} {z}
|
||||
// CHECK: encoding: [0x62,0x81,0x7e,0xab,0x16,0xd0]
|
||||
vmovshdup %ymm24, %ymm18 {%k3} {z}
|
||||
|
||||
// CHECK: vmovshdup (%rcx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x28,0x16,0x11]
|
||||
vmovshdup (%rcx), %ymm18
|
||||
|
||||
// CHECK: vmovshdup 291(%rax,%r14,8), %ymm18
|
||||
// CHECK: encoding: [0x62,0xa1,0x7e,0x28,0x16,0x94,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovshdup 291(%rax,%r14,8), %ymm18
|
||||
|
||||
// CHECK: vmovshdup 4064(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x28,0x16,0x52,0x7f]
|
||||
vmovshdup 4064(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovshdup 4096(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x28,0x16,0x92,0x00,0x10,0x00,0x00]
|
||||
vmovshdup 4096(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovshdup -4096(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x28,0x16,0x52,0x80]
|
||||
vmovshdup -4096(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovshdup -4128(%rdx), %ymm18
|
||||
// CHECK: encoding: [0x62,0xe1,0x7e,0x28,0x16,0x92,0xe0,0xef,0xff,0xff]
|
||||
vmovshdup -4128(%rdx), %ymm18
|
||||
|
||||
// CHECK: vmovsldup %xmm21, %xmm25
|
||||
// CHECK: encoding: [0x62,0x21,0x7e,0x08,0x12,0xcd]
|
||||
vmovsldup %xmm21, %xmm25
|
||||
|
||||
// CHECK: vmovsldup %xmm21, %xmm25 {%k5}
|
||||
// CHECK: encoding: [0x62,0x21,0x7e,0x0d,0x12,0xcd]
|
||||
vmovsldup %xmm21, %xmm25 {%k5}
|
||||
|
||||
// CHECK: vmovsldup %xmm21, %xmm25 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0x21,0x7e,0x8d,0x12,0xcd]
|
||||
vmovsldup %xmm21, %xmm25 {%k5} {z}
|
||||
|
||||
// CHECK: vmovsldup (%rcx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x08,0x12,0x09]
|
||||
vmovsldup (%rcx), %xmm25
|
||||
|
||||
// CHECK: vmovsldup 291(%rax,%r14,8), %xmm25
|
||||
// CHECK: encoding: [0x62,0x21,0x7e,0x08,0x12,0x8c,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovsldup 291(%rax,%r14,8), %xmm25
|
||||
|
||||
// CHECK: vmovsldup 2032(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x08,0x12,0x4a,0x7f]
|
||||
vmovsldup 2032(%rdx), %xmm25
|
||||
|
||||
// CHECK: vmovsldup 2048(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x08,0x12,0x8a,0x00,0x08,0x00,0x00]
|
||||
vmovsldup 2048(%rdx), %xmm25
|
||||
|
||||
// CHECK: vmovsldup -2048(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x08,0x12,0x4a,0x80]
|
||||
vmovsldup -2048(%rdx), %xmm25
|
||||
|
||||
// CHECK: vmovsldup -2064(%rdx), %xmm25
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x08,0x12,0x8a,0xf0,0xf7,0xff,0xff]
|
||||
vmovsldup -2064(%rdx), %xmm25
|
||||
|
||||
// CHECK: vmovsldup %ymm29, %ymm24
|
||||
// CHECK: encoding: [0x62,0x01,0x7e,0x28,0x12,0xc5]
|
||||
vmovsldup %ymm29, %ymm24
|
||||
|
||||
// CHECK: vmovsldup %ymm29, %ymm24 {%k5}
|
||||
// CHECK: encoding: [0x62,0x01,0x7e,0x2d,0x12,0xc5]
|
||||
vmovsldup %ymm29, %ymm24 {%k5}
|
||||
|
||||
// CHECK: vmovsldup %ymm29, %ymm24 {%k5} {z}
|
||||
// CHECK: encoding: [0x62,0x01,0x7e,0xad,0x12,0xc5]
|
||||
vmovsldup %ymm29, %ymm24 {%k5} {z}
|
||||
|
||||
// CHECK: vmovsldup (%rcx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x28,0x12,0x01]
|
||||
vmovsldup (%rcx), %ymm24
|
||||
|
||||
// CHECK: vmovsldup 291(%rax,%r14,8), %ymm24
|
||||
// CHECK: encoding: [0x62,0x21,0x7e,0x28,0x12,0x84,0xf0,0x23,0x01,0x00,0x00]
|
||||
vmovsldup 291(%rax,%r14,8), %ymm24
|
||||
|
||||
// CHECK: vmovsldup 4064(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x28,0x12,0x42,0x7f]
|
||||
vmovsldup 4064(%rdx), %ymm24
|
||||
|
||||
// CHECK: vmovsldup 4096(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x28,0x12,0x82,0x00,0x10,0x00,0x00]
|
||||
vmovsldup 4096(%rdx), %ymm24
|
||||
|
||||
// CHECK: vmovsldup -4096(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x28,0x12,0x42,0x80]
|
||||
vmovsldup -4096(%rdx), %ymm24
|
||||
|
||||
// CHECK: vmovsldup -4128(%rdx), %ymm24
|
||||
// CHECK: encoding: [0x62,0x61,0x7e,0x28,0x12,0x82,0xe0,0xef,0xff,0xff]
|
||||
vmovsldup -4128(%rdx), %ymm24
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user