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[AArch64] Add ARMv8.2-A Statistical Profiling Extension
The Statistical Profiling Extension is an optional extension to ARMv8.2-A. Since it is an optional extension, I have added the FeatureSPE subtarget feature to control it. The assembler-visible parts of this extension are the new "psb csync" instruction, which is equivalent to "hint #17", and a number of system registers. Differential Revision: http://reviews.llvm.org/D15021 llvm-svn: 254401
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@ -38,6 +38,9 @@ def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Full FP16", [FeatureFPARMv8]>;
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def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
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"Enable Statistical Profiling extension">;
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/// Cyclone has register move instructions which are "free".
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zero-cycle register moves">;
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@ -911,6 +911,25 @@ def msr_sysreg_op : Operand<i32> {
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let PrintMethod = "printMSRSystemRegister";
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}
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def PSBHintOperand : AsmOperandClass {
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let Name = "PSBHint";
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let ParserMethod = "tryParsePSBHint";
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}
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def psbhint_op : Operand<i32> {
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let ParserMatchClass = PSBHintOperand;
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let PrintMethod = "printPSBHintOp";
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let MCOperandPredicate = [{
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// Check, if operand is valid, to fix exhaustive aliasing in disassembly.
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// "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
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if (!MCOp.isImm())
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return false;
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bool ValidNamed;
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(void)AArch64PSBHint::PSBHintMapper().toString(MCOp.getImm(),
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STI.getFeatureBits(), ValidNamed);
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return ValidNamed;
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}];
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}
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class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
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"mrs", "\t$Rt, $systemreg"> {
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bits<16> systemreg;
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@ -29,6 +29,8 @@ def HasCRC : Predicate<"Subtarget->hasCRC()">,
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def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
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def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
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AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
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def HasSPE : Predicate<"Subtarget->hasSPE()">,
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AssemblerPredicate<"FeatureSPE", "spe">;
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def IsLE : Predicate<"Subtarget->isLittleEndian()">;
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def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
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@ -382,6 +384,9 @@ def : InstAlias<"wfi", (HINT 0b011)>;
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def : InstAlias<"sev", (HINT 0b100)>;
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def : InstAlias<"sevl", (HINT 0b101)>;
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// v8.2a Statistical Profiling extension
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def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
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// As far as LLVM is concerned this writes to the system's exclusive monitors.
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let mayLoad = 1, mayStore = 1 in
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def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
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@ -47,6 +47,7 @@ protected:
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bool HasCRC;
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bool HasPerfMon;
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bool HasFullFP16;
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bool HasSPE;
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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bool HasZeroCycleRegMove;
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@ -124,6 +125,7 @@ public:
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bool hasPerfMon() const { return HasPerfMon; }
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bool hasFullFP16() const { return HasFullFP16; }
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bool hasSPE() const { return HasSPE; }
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bool isLittleEndian() const { return IsLittle; }
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@ -100,6 +100,7 @@ private:
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OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
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OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
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OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
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OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);
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OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
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OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
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OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
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@ -159,7 +160,8 @@ private:
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k_Prefetch,
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k_ShiftExtend,
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k_FPImm,
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k_Barrier
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k_Barrier,
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k_PSBHint,
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} Kind;
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SMLoc StartLoc, EndLoc;
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@ -227,6 +229,12 @@ private:
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unsigned Length;
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};
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struct PSBHintOp {
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unsigned Val;
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const char *Data;
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unsigned Length;
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};
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struct ShiftExtendOp {
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AArch64_AM::ShiftExtendType Type;
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unsigned Amount;
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@ -250,6 +258,7 @@ private:
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struct SysRegOp SysReg;
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struct SysCRImmOp SysCRImm;
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struct PrefetchOp Prefetch;
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struct PSBHintOp PSBHint;
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struct ShiftExtendOp ShiftExtend;
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};
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@ -301,6 +310,9 @@ public:
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case k_Prefetch:
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Prefetch = o.Prefetch;
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break;
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case k_PSBHint:
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PSBHint = o.PSBHint;
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break;
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case k_ShiftExtend:
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ShiftExtend = o.ShiftExtend;
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break;
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@ -392,6 +404,16 @@ public:
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return Prefetch.Val;
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}
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unsigned getPSBHint() const {
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assert(Kind == k_PSBHint && "Invalid access!");
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return PSBHint.Val;
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}
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StringRef getPSBHintName() const {
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assert(Kind == k_PSBHint && "Invalid access!");
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return StringRef(PSBHint.Data, PSBHint.Length);
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}
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StringRef getPrefetchName() const {
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assert(Kind == k_Prefetch && "Invalid access!");
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return StringRef(Prefetch.Data, Prefetch.Length);
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@ -961,6 +983,7 @@ public:
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}
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bool isSysCR() const { return Kind == k_SysCR; }
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bool isPrefetch() const { return Kind == k_Prefetch; }
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bool isPSBHint() const { return Kind == k_PSBHint; }
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bool isShiftExtend() const { return Kind == k_ShiftExtend; }
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bool isShifter() const {
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if (!isShiftExtend())
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@ -1534,6 +1557,11 @@ public:
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Inst.addOperand(MCOperand::createImm(getPrefetch()));
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}
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void addPSBHintOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createImm(getPSBHint()));
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}
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void addShifterOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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unsigned Imm =
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@ -1730,6 +1758,19 @@ public:
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return Op;
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}
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static std::unique_ptr<AArch64Operand> CreatePSBHint(unsigned Val,
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StringRef Str,
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SMLoc S,
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MCContext &Ctx) {
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auto Op = make_unique<AArch64Operand>(k_PSBHint, Ctx);
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Op->PSBHint.Val = Val;
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Op->PSBHint.Data = Str.data();
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Op->PSBHint.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static std::unique_ptr<AArch64Operand>
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CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val,
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bool HasExplicitAmount, SMLoc S, SMLoc E, MCContext &Ctx) {
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@ -1803,6 +1844,10 @@ void AArch64Operand::print(raw_ostream &OS) const {
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OS << "<prfop invalid #" << getPrefetch() << ">";
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break;
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}
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case k_PSBHint: {
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OS << getPSBHintName();
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break;
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}
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case k_ShiftExtend: {
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OS << "<" << AArch64_AM::getShiftExtendName(getShiftExtendType()) << " #"
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<< getShiftExtendAmount();
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@ -2069,6 +2114,32 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
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return MatchOperand_Success;
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}
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/// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
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AArch64AsmParser::OperandMatchResultTy
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AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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SMLoc S = getLoc();
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const AsmToken &Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier)) {
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TokError("invalid operand for instruction");
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return MatchOperand_ParseFail;
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}
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bool Valid;
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auto Mapper = AArch64PSBHint::PSBHintMapper();
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unsigned psbhint =
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Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
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if (!Valid) {
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TokError("invalid operand for instruction");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat identifier token.
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Operands.push_back(AArch64Operand::CreatePSBHint(psbhint, Tok.getString(),
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S, getContext()));
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return MatchOperand_Success;
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}
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/// tryParseAdrpLabel - Parse and validate a source label for the ADRP
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/// instruction.
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AArch64AsmParser::OperandMatchResultTy
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@ -1144,6 +1144,19 @@ void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
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O << '#' << prfop;
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}
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void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned psbhintop = MI->getOperand(OpNum).getImm();
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bool Valid;
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StringRef Name =
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AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid);
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if (Valid)
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O << Name;
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else
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O << '#' << psbhintop;
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}
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void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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void printPrefetchOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printPSBHintOp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printFPImmOperand(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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AArch64PState::PStateMapper::PStateMapper()
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: AArch64NamedImmMapper(PStateMappings, 0) {}
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const AArch64NamedImmMapper::Mapping AArch64PSBHint::PSBHintMapper::PSBHintMappings[] = {
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// v8.2a "Statistical Profiling" extension-specific PSB operand
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{"csync", CSync, {AArch64::FeatureSPE}},
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};
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AArch64PSBHint::PSBHintMapper::PSBHintMapper()
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: AArch64NamedImmMapper(PSBHintMappings, 0) {}
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const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
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{"mdccsr_el0", MDCCSR_EL0, {}},
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{"dbgdtrrx_el0", DBGDTRRX_EL0, {}},
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@ -808,6 +816,21 @@ const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings
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// v8.2a registers
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{"uao", UAO, {AArch64::HasV8_2aOps}},
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// v8.2a "Statistical Profiling extension" registers
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{"pmblimitr_el1", PMBLIMITR_EL1, {AArch64::FeatureSPE}},
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{"pmbptr_el1", PMBPTR_EL1, {AArch64::FeatureSPE}},
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{"pmbsr_el1", PMBSR_EL1, {AArch64::FeatureSPE}},
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{"pmbidr_el1", PMBIDR_EL1, {AArch64::FeatureSPE}},
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{"pmscr_el2", PMSCR_EL2, {AArch64::FeatureSPE}},
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{"pmscr_el12", PMSCR_EL12, {AArch64::FeatureSPE}},
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{"pmscr_el1", PMSCR_EL1, {AArch64::FeatureSPE}},
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{"pmsicr_el1", PMSICR_EL1, {AArch64::FeatureSPE}},
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{"pmsirr_el1", PMSIRR_EL1, {AArch64::FeatureSPE}},
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{"pmsfcr_el1", PMSFCR_EL1, {AArch64::FeatureSPE}},
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{"pmsevfr_el1", PMSEVFR_EL1, {AArch64::FeatureSPE}},
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{"pmslatfr_el1", PMSLATFR_EL1, {AArch64::FeatureSPE}},
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{"pmsidr_el1", PMSIDR_EL1, {AArch64::FeatureSPE}},
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};
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uint32_t
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@ -478,6 +478,21 @@ namespace AArch64PState {
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}
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namespace AArch64PSBHint {
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enum PSBHintValues {
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Invalid = -1,
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// v8.2a "Statistical Profiling" extension-specific PSB operands
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CSync = 0x11, // psb csync = hint #0x11
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};
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struct PSBHintMapper : AArch64NamedImmMapper {
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const static Mapping PSBHintMappings[];
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PSBHintMapper();
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};
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}
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namespace AArch64SE {
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enum ShiftExtSpecifiers {
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Invalid = -1,
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@ -1199,6 +1214,21 @@ namespace AArch64SysReg {
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// v8.2a registers
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UAO = 0xc214, // 11 000 0100 0010 100
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// v8.2a "Statistical Profiling extension" registers
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PMBLIMITR_EL1 = 0xc4d0, // 11 000 1001 1010 000
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PMBPTR_EL1 = 0xc4d1, // 11 000 1001 1010 001
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PMBSR_EL1 = 0xc4d3, // 11 000 1001 1010 011
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PMBIDR_EL1 = 0xc4d7, // 11 000 1001 1010 111
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PMSCR_EL2 = 0xe4c8, // 11 100 1001 1001 000
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PMSCR_EL12 = 0xecc8, // 11 101 1001 1001 000
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PMSCR_EL1 = 0xc4c8, // 11 000 1001 1001 000
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PMSICR_EL1 = 0xc4ca, // 11 000 1001 1001 010
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PMSIRR_EL1 = 0xc4cb, // 11 000 1001 1001 011
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PMSFCR_EL1 = 0xc4cc, // 11 000 1001 1001 100
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PMSEVFR_EL1 = 0xc4cd, // 11 000 1001 1001 101
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PMSLATFR_EL1 = 0xc4ce, // 11 000 1001 1001 110
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PMSIDR_EL1 = 0xc4cf, // 11 000 1001 1001 111
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// Cyclone specific system registers
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CPM_IOACC_CTL_EL3 = 0xff90,
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};
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87
test/MC/AArch64/armv8.2a-statistical-profiling.s
Normal file
87
test/MC/AArch64/armv8.2a-statistical-profiling.s
Normal file
@ -0,0 +1,87 @@
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe < %s | FileCheck %s
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=NO_SPE %s
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psb csync
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// CHECK: psb csync // encoding: [0x3f,0x22,0x03,0xd5]
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// NO_SPE: invalid operand for instruction
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msr pmblimitr_el1, x0
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msr pmbptr_el1, x0
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msr pmbsr_el1, x0
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msr pmbidr_el1, x0
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msr pmscr_el2, x0
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msr pmscr_el12, x0
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msr pmscr_el1, x0
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msr pmsicr_el1, x0
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msr pmsirr_el1, x0
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msr pmsfcr_el1, x0
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msr pmsevfr_el1, x0
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msr pmslatfr_el1, x0
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msr pmsidr_el1, x0
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// CHECK: msr PMBLIMITR_EL1, x0 // encoding: [0x00,0x9a,0x18,0xd5]
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// CHECK: msr PMBPTR_EL1, x0 // encoding: [0x20,0x9a,0x18,0xd5]
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// CHECK: msr PMBSR_EL1, x0 // encoding: [0x60,0x9a,0x18,0xd5]
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// CHECK: msr PMBIDR_EL1, x0 // encoding: [0xe0,0x9a,0x18,0xd5]
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// CHECK: msr PMSCR_EL2, x0 // encoding: [0x00,0x99,0x1c,0xd5]
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// CHECK: msr PMSCR_EL12, x0 // encoding: [0x00,0x99,0x1d,0xd5]
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// CHECK: msr PMSCR_EL1, x0 // encoding: [0x00,0x99,0x18,0xd5]
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// CHECK: msr PMSICR_EL1, x0 // encoding: [0x40,0x99,0x18,0xd5]
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// CHECK: msr PMSIRR_EL1, x0 // encoding: [0x60,0x99,0x18,0xd5]
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// CHECK: msr PMSFCR_EL1, x0 // encoding: [0x80,0x99,0x18,0xd5]
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// CHECK: msr PMSEVFR_EL1, x0 // encoding: [0xa0,0x99,0x18,0xd5]
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// CHECK: msr PMSLATFR_EL1, x0 // encoding: [0xc0,0x99,0x18,0xd5]
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// CHECK: msr PMSIDR_EL1, x0 // encoding: [0xe0,0x99,0x18,0xd5]
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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// NO_SPE: error: expected writable system register or pstate
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mrs x0, pmblimitr_el1
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mrs x0, pmbptr_el1
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mrs x0, pmbsr_el1
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mrs x0, pmbidr_el1
|
||||
mrs x0, pmscr_el2
|
||||
mrs x0, pmscr_el12
|
||||
mrs x0, pmscr_el1
|
||||
mrs x0, pmsicr_el1
|
||||
mrs x0, pmsirr_el1
|
||||
mrs x0, pmsfcr_el1
|
||||
mrs x0, pmsevfr_el1
|
||||
mrs x0, pmslatfr_el1
|
||||
mrs x0, pmsidr_el1
|
||||
|
||||
// CHECK: mrs x0, PMBLIMITR_EL1 // encoding: [0x00,0x9a,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMBPTR_EL1 // encoding: [0x20,0x9a,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMBSR_EL1 // encoding: [0x60,0x9a,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMBIDR_EL1 // encoding: [0xe0,0x9a,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSCR_EL2 // encoding: [0x00,0x99,0x3c,0xd5]
|
||||
// CHECK: mrs x0, PMSCR_EL12 // encoding: [0x00,0x99,0x3d,0xd5]
|
||||
// CHECK: mrs x0, PMSCR_EL1 // encoding: [0x00,0x99,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSICR_EL1 // encoding: [0x40,0x99,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSIRR_EL1 // encoding: [0x60,0x99,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSFCR_EL1 // encoding: [0x80,0x99,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSEVFR_EL1 // encoding: [0xa0,0x99,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSLATFR_EL1 // encoding: [0xc0,0x99,0x38,0xd5]
|
||||
// CHECK: mrs x0, PMSIDR_EL1 // encoding: [0xe0,0x99,0x38,0xd5]
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
||||
// NO_SPE: error: expected readable system register
|
@ -0,0 +1,91 @@
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+spe --disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck --check-prefix=NO_SPE %s
|
||||
|
||||
[0x1f,0x22,0x03,0xd5]
|
||||
# CHECK: hint #0x10
|
||||
# NO_SPE: hint #0x10
|
||||
|
||||
[0x3f,0x22,0x03,0xd5]
|
||||
# CHECK: psb csync
|
||||
# NO_SPE: hint #0x11
|
||||
|
||||
[0x00,0x9a,0x18,0xd5]
|
||||
[0x20,0x9a,0x18,0xd5]
|
||||
[0x60,0x9a,0x18,0xd5]
|
||||
[0xe0,0x9a,0x18,0xd5]
|
||||
[0x00,0x99,0x1c,0xd5]
|
||||
[0x00,0x99,0x1d,0xd5]
|
||||
[0x00,0x99,0x18,0xd5]
|
||||
[0x40,0x99,0x18,0xd5]
|
||||
[0x60,0x99,0x18,0xd5]
|
||||
[0x80,0x99,0x18,0xd5]
|
||||
[0xa0,0x99,0x18,0xd5]
|
||||
[0xc0,0x99,0x18,0xd5]
|
||||
[0xe0,0x99,0x18,0xd5]
|
||||
# CHECK: msr PMBLIMITR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C10_0, x0
|
||||
# CHECK: msr PMBPTR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C10_1, x0
|
||||
# CHECK: msr PMBSR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C10_3, x0
|
||||
# CHECK: msr PMBIDR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C10_7, x0
|
||||
# CHECK: msr PMSCR_EL2, x0
|
||||
# NO_SPE: msr S3_4_C9_C9_0, x0
|
||||
# CHECK: msr PMSCR_EL12, x0
|
||||
# NO_SPE: msr S3_5_C9_C9_0, x0
|
||||
# CHECK: msr PMSCR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_0, x0
|
||||
# CHECK: msr PMSICR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_2, x0
|
||||
# CHECK: msr PMSIRR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_3, x0
|
||||
# CHECK: msr PMSFCR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_4, x0
|
||||
# CHECK: msr PMSEVFR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_5, x0
|
||||
# CHECK: msr PMSLATFR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_6, x0
|
||||
# CHECK: msr PMSIDR_EL1, x0
|
||||
# NO_SPE: msr S3_0_C9_C9_7, x0
|
||||
|
||||
[0x00,0x9a,0x38,0xd5]
|
||||
[0x20,0x9a,0x38,0xd5]
|
||||
[0x60,0x9a,0x38,0xd5]
|
||||
[0xe0,0x9a,0x38,0xd5]
|
||||
[0x00,0x99,0x3c,0xd5]
|
||||
[0x00,0x99,0x3d,0xd5]
|
||||
[0x00,0x99,0x38,0xd5]
|
||||
[0x40,0x99,0x38,0xd5]
|
||||
[0x60,0x99,0x38,0xd5]
|
||||
[0x80,0x99,0x38,0xd5]
|
||||
[0xa0,0x99,0x38,0xd5]
|
||||
[0xc0,0x99,0x38,0xd5]
|
||||
[0xe0,0x99,0x38,0xd5]
|
||||
|
||||
# CHECK: mrs x0, PMBLIMITR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C10_0
|
||||
# CHECK: mrs x0, PMBPTR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C10_1
|
||||
# CHECK: mrs x0, PMBSR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C10_3
|
||||
# CHECK: mrs x0, PMBIDR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C10_7
|
||||
# CHECK: mrs x0, PMSCR_EL2
|
||||
# NO_SPE: mrs x0, S3_4_C9_C9_0
|
||||
# CHECK: mrs x0, PMSCR_EL12
|
||||
# NO_SPE: mrs x0, S3_5_C9_C9_0
|
||||
# CHECK: mrs x0, PMSCR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_0
|
||||
# CHECK: mrs x0, PMSICR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_2
|
||||
# CHECK: mrs x0, PMSIRR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_3
|
||||
# CHECK: mrs x0, PMSFCR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_4
|
||||
# CHECK: mrs x0, PMSEVFR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_5
|
||||
# CHECK: mrs x0, PMSLATFR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_6
|
||||
# CHECK: mrs x0, PMSIDR_EL1
|
||||
# NO_SPE: mrs x0, S3_0_C9_C9_7
|
@ -901,7 +901,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
|
||||
break; // No conditions on this operand at all
|
||||
}
|
||||
Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
|
||||
Op + ", " + llvm::utostr(Entry) + ")";
|
||||
Op + ", STI, " + llvm::utostr(Entry) + ")";
|
||||
}
|
||||
// for all subcases of ResultOperand::K_Record:
|
||||
IAP.addCond(Cond);
|
||||
@ -996,8 +996,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
|
||||
|
||||
if (!MCOpPredicates.empty())
|
||||
O << "static bool " << Target.getName() << ClassName
|
||||
<< "ValidateMCOperand(\n"
|
||||
<< " const MCOperand &MCOp, unsigned PredicateIndex);\n";
|
||||
<< "ValidateMCOperand(const MCOperand &MCOp,\n"
|
||||
<< " const MCSubtargetInfo &STI,\n"
|
||||
<< " unsigned PredicateIndex);\n";
|
||||
|
||||
O << HeaderO.str();
|
||||
O.indent(2) << "const char *AsmString;\n";
|
||||
@ -1069,8 +1070,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
|
||||
|
||||
if (!MCOpPredicates.empty()) {
|
||||
O << "static bool " << Target.getName() << ClassName
|
||||
<< "ValidateMCOperand(\n"
|
||||
<< " const MCOperand &MCOp, unsigned PredicateIndex) {\n"
|
||||
<< "ValidateMCOperand(const MCOperand &MCOp,\n"
|
||||
<< " const MCSubtargetInfo &STI,\n"
|
||||
<< " unsigned PredicateIndex) {\n"
|
||||
<< " switch (PredicateIndex) {\n"
|
||||
<< " default:\n"
|
||||
<< " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
|
||||
|
Loading…
Reference in New Issue
Block a user