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[ARM] Add predicated add reduction patterns
Given a vecreduce.add(select(p, x, 0)), we can convert that to a predicated vaddv, as the else value for the select is the identity value, a zero. That is what this patch does for the vaddv, vaddva, vaddlv and vaddlva instructions, copying the existing patterns to also handle predication through a select. Differential Revision: https://reviews.llvm.org/D84101
This commit is contained in:
David Green
parent
b4f9e0d70d
commit
030e640555
@ -1718,6 +1718,8 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VMULLu: return "ARMISD::VMULLu";
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case ARMISD::VADDVs: return "ARMISD::VADDVs";
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case ARMISD::VADDVu: return "ARMISD::VADDVu";
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case ARMISD::VADDVps: return "ARMISD::VADDVps";
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case ARMISD::VADDVpu: return "ARMISD::VADDVpu";
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case ARMISD::VADDLVs: return "ARMISD::VADDLVs";
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case ARMISD::VADDLVu: return "ARMISD::VADDLVu";
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case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs";
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@ -14729,6 +14731,20 @@ static SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
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return A;
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return SDValue();
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};
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auto IsPredVADDV = [&](MVT RetTy, unsigned ExtendCode,
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ArrayRef<MVT> ExtTypes, SDValue &Mask) {
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if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT ||
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!ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode()))
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return SDValue();
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Mask = N0->getOperand(0);
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SDValue Ext = N0->getOperand(1);
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if (Ext->getOpcode() != ExtendCode)
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return SDValue();
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SDValue A = Ext->getOperand(0);
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if (llvm::any_of(ExtTypes, [&A](MVT Ty) { return A.getValueType() == Ty; }))
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return A;
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return SDValue();
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};
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auto IsVMLAV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef<MVT> ExtTypes,
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SDValue &A, SDValue &B) {
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if (ResVT != RetTy || N0->getOpcode() != ISD::MUL)
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@ -14759,6 +14775,16 @@ static SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
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if (SDValue A = IsVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32}))
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return Create64bitNode(ARMISD::VADDLVu, {A});
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SDValue Mask;
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if (SDValue A = IsPredVADDV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, Mask))
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return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask);
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if (SDValue A = IsPredVADDV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}, Mask))
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return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask);
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if (SDValue A = IsPredVADDV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v4i32}, Mask))
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return Create64bitNode(ARMISD::VADDLVps, {A, Mask});
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if (SDValue A = IsPredVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32}, Mask))
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return Create64bitNode(ARMISD::VADDLVpu, {A, Mask});
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SDValue A, B;
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if (IsVMLAV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B))
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return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B);
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@ -219,14 +219,16 @@ class VectorType;
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// MVE reductions
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VADDVs, // sign- or zero-extend the elements of a vector to i32,
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VADDVu, // add them all together, and return an i32 of their sum
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VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask
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VADDVpu,
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VADDLVs, // sign- or zero-extend elements to i64 and sum, returning
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VADDLVu, // the low and high 32-bit halves of the sum
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VADDLVAs, // same as VADDLV[su] but also add an input accumulator
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VADDLVAs, // Same as VADDLV[su] but also add an input accumulator
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VADDLVAu, // provided as low and high halves
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VADDLVps, // same as VADDLVs but with a v4i1 predicate mask
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VADDLVpu, // same as VADDLVu but with a v4i1 predicate mask
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VADDLVAps, // same as VADDLVps but with a v4i1 predicate mask
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VADDLVApu, // same as VADDLVpu but with a v4i1 predicate mask
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VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask
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VADDLVpu,
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VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
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VADDLVApu,
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VMLAVs,
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VMLAVu,
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VMLALVs,
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@ -684,8 +684,13 @@ class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
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let validForTailPredication = 1;
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}
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def SDTVecReduceP : SDTypeProfile<1, 2, [ // VADDLVp
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SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2>
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]>;
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def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
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def ARMVADDVu : SDNode<"ARMISD::VADDVu", SDTVecReduce>;
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def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>;
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def ARMVADDVpu : SDNode<"ARMISD::VADDVpu", SDTVecReduceP>;
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multiclass MVE_VADDV_A<MVEVectorVTInfo VTI> {
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def acc : MVE_VADDV<"vaddva", VTI.Suffix,
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@ -702,20 +707,39 @@ multiclass MVE_VADDV_A<MVEVectorVTInfo VTI> {
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if VTI.Unsigned then {
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def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
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(i32 (InstN $vec))>;
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def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
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(VTI.Vec MQPR:$vec),
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(VTI.Vec ARMimmAllZerosV))))),
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(i32 (InstN $vec, ARMVCCThen, $pred))>;
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def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
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(i32 (InstN $vec))>;
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def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
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(i32 (InstN $vec, ARMVCCThen, $pred))>;
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def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))),
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(i32 tGPREven:$acc))),
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(i32 (InstA $acc, $vec))>;
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def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred),
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(VTI.Vec MQPR:$vec),
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(VTI.Vec ARMimmAllZerosV))))),
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(i32 tGPREven:$acc))),
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(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
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def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))),
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(i32 tGPREven:$acc))),
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(i32 (InstA $acc, $vec))>;
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def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
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(i32 tGPREven:$acc))),
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(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
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} else {
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def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
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(i32 (InstN $vec))>;
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def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))),
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(i32 tGPREven:$acc))),
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(i32 (InstA $acc, $vec))>;
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def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
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(i32 (InstN $vec, ARMVCCThen, $pred))>;
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def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))),
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(i32 tGPREven:$acc))),
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(i32 (InstA $acc, $vec, ARMVCCThen, $pred))>;
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}
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def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec),
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File diff suppressed because it is too large
Load Diff
@ -4,10 +4,9 @@
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define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) {
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; CHECK-LABEL: add_v4i32_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q3, #0x0
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; CHECK-NEXT: vmul.i32 q0, q0, q1
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; CHECK-NEXT: vpt.i32 eq, q2, zr
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; CHECK-NEXT: vmult.i32 q3, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q3
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; CHECK-NEXT: vaddvt.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp eq <4 x i32> %b, zeroinitializer
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@ -381,14 +380,10 @@ entry:
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define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) {
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; CHECK-LABEL: add_v4i16_v4i32_zext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q2, q2
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; CHECK-NEXT: vmovlb.u16 q1, q1
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; CHECK-NEXT: vcmp.i32 eq, q2, zr
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmult.i32 q2, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q2
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; CHECK-NEXT: vmullb.u16 q0, q0, q1
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; CHECK-NEXT: vmovlb.u16 q1, q2
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; CHECK-NEXT: vpt.i32 eq, q1, zr
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; CHECK-NEXT: vaddvt.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp eq <4 x i16> %b, zeroinitializer
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@ -403,14 +398,10 @@ entry:
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define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) {
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; CHECK-LABEL: add_v4i16_v4i32_sext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q2, q2
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: vcmp.i32 eq, q2, zr
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmult.i32 q2, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q2
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; CHECK-NEXT: vmullb.s16 q0, q0, q1
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; CHECK-NEXT: vmovlb.u16 q1, q2
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; CHECK-NEXT: vpt.i32 eq, q1, zr
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; CHECK-NEXT: vaddvt.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp eq <4 x i16> %b, zeroinitializer
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@ -425,10 +416,9 @@ entry:
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define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) {
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; CHECK-LABEL: add_v8i16_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q3, #0x0
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; CHECK-NEXT: vmul.i16 q0, q0, q1
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; CHECK-NEXT: vpt.i16 eq, q2, zr
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; CHECK-NEXT: vmult.i16 q3, q0, q1
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; CHECK-NEXT: vaddv.u16 r0, q3
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; CHECK-NEXT: vaddvt.u16 r0, q0
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: bx lr
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entry:
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@ -1290,14 +1280,12 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %y, <4 x i
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; CHECK-LABEL: add_v4i8_v4i32_zext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q3, #0xff
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; CHECK-NEXT: vand q2, q2, q3
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; CHECK-NEXT: vand q1, q1, q3
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; CHECK-NEXT: vcmp.i32 eq, q2, zr
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vand q0, q0, q3
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmult.i32 q2, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q2
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; CHECK-NEXT: vmul.i32 q0, q0, q1
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; CHECK-NEXT: vand q1, q2, q3
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; CHECK-NEXT: vpt.i32 eq, q1, zr
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; CHECK-NEXT: vaddvt.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp eq <4 x i8> %b, zeroinitializer
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@ -1312,17 +1300,15 @@ entry:
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define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) {
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; CHECK-LABEL: add_v4i8_v4i32_sext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q3, #0xff
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: vand q2, q2, q3
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: vcmp.i32 eq, q2, zr
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmult.i32 q2, q0, q1
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; CHECK-NEXT: vaddv.u32 r0, q2
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; CHECK-NEXT: vmul.i32 q0, q0, q1
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; CHECK-NEXT: vmov.i32 q1, #0xff
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; CHECK-NEXT: vand q1, q2, q1
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; CHECK-NEXT: vpt.i32 eq, q1, zr
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; CHECK-NEXT: vaddvt.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp eq <4 x i8> %b, zeroinitializer
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@ -1593,14 +1579,10 @@ entry:
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define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) {
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; CHECK-LABEL: add_v8i8_v8i16_zext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q2, q2
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; CHECK-NEXT: vmovlb.u8 q1, q1
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; CHECK-NEXT: vcmp.i16 eq, q2, zr
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmult.i16 q2, q0, q1
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; CHECK-NEXT: vaddv.u16 r0, q2
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; CHECK-NEXT: vmullb.u8 q0, q0, q1
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; CHECK-NEXT: vmovlb.u8 q1, q2
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; CHECK-NEXT: vpt.i16 eq, q1, zr
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; CHECK-NEXT: vaddvt.u16 r0, q0
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; CHECK-NEXT: uxth r0, r0
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; CHECK-NEXT: bx lr
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entry:
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@ -1616,14 +1598,10 @@ entry:
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define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) {
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; CHECK-LABEL: add_v8i8_v8i16_sext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q2, q2
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: vcmp.i16 eq, q2, zr
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; CHECK-NEXT: vmov.i32 q2, #0x0
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmult.i16 q2, q0, q1
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; CHECK-NEXT: vaddv.u16 r0, q2
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; CHECK-NEXT: vmullb.s8 q0, q0, q1
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; CHECK-NEXT: vmovlb.u8 q1, q2
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; CHECK-NEXT: vpt.i16 eq, q1, zr
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; CHECK-NEXT: vaddvt.u16 r0, q0
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; CHECK-NEXT: sxth r0, r0
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; CHECK-NEXT: bx lr
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entry:
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@ -1639,10 +1617,9 @@ entry:
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define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) {
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; CHECK-LABEL: add_v16i8_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q3, #0x0
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; CHECK-NEXT: vmul.i8 q0, q0, q1
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; CHECK-NEXT: vpt.i8 eq, q2, zr
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; CHECK-NEXT: vmult.i8 q3, q0, q1
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; CHECK-NEXT: vaddv.u8 r0, q3
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; CHECK-NEXT: vaddvt.u8 r0, q0
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; CHECK-NEXT: uxtb r0, r0
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; CHECK-NEXT: bx lr
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entry:
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@ -2567,10 +2544,9 @@ entry:
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define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i32 %a) {
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; CHECK-LABEL: add_v4i32_v4i32_acc:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q3, #0x0
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; CHECK-NEXT: vmul.i32 q0, q0, q1
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; CHECK-NEXT: vpt.i32 eq, q2, zr
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; CHECK-NEXT: vmult.i32 q3, q0, q1
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; CHECK-NEXT: vaddva.u32 r0, q3
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; CHECK-NEXT: vaddvat.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%c = icmp eq <4 x i32> %b, zeroinitializer
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@ -2967,14 +2943,10 @@ entry:
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define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) {
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; CHECK-LABEL: add_v4i16_v4i32_acc_zext:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q2, q2
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; CHECK-NEXT: vmovlb.u16 q1, q1
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||||
; CHECK-NEXT: vcmp.i32 eq, q2, zr
|
||||
; CHECK-NEXT: vmov.i32 q2, #0x0
|
||||
; CHECK-NEXT: vmovlb.u16 q0, q0
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmult.i32 q2, q0, q1
|
||||
; CHECK-NEXT: vaddva.u32 r0, q2
|
||||
; CHECK-NEXT: vmullb.u16 q0, q0, q1
|
||||
; CHECK-NEXT: vmovlb.u16 q1, q2
|
||||
; CHECK-NEXT: vpt.i32 eq, q1, zr
|
||||
; CHECK-NEXT: vaddvat.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%c = icmp eq <4 x i16> %b, zeroinitializer
|
||||
@ -2990,14 +2962,10 @@ entry:
|
||||
define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) {
|
||||
; CHECK-LABEL: add_v4i16_v4i32_acc_sext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovlb.u16 q2, q2
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q1
|
||||
; CHECK-NEXT: vcmp.i32 eq, q2, zr
|
||||
; CHECK-NEXT: vmov.i32 q2, #0x0
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmult.i32 q2, q0, q1
|
||||
; CHECK-NEXT: vaddva.u32 r0, q2
|
||||
; CHECK-NEXT: vmullb.s16 q0, q0, q1
|
||||
; CHECK-NEXT: vmovlb.u16 q1, q2
|
||||
; CHECK-NEXT: vpt.i32 eq, q1, zr
|
||||
; CHECK-NEXT: vaddvat.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%c = icmp eq <4 x i16> %b, zeroinitializer
|
||||
@ -3013,10 +2981,9 @@ entry:
|
||||
define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i16 %a) {
|
||||
; CHECK-LABEL: add_v8i16_v8i16_acc:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i32 q3, #0x0
|
||||
; CHECK-NEXT: vmul.i16 q0, q0, q1
|
||||
; CHECK-NEXT: vpt.i16 eq, q2, zr
|
||||
; CHECK-NEXT: vmult.i16 q3, q0, q1
|
||||
; CHECK-NEXT: vaddva.u16 r0, q3
|
||||
; CHECK-NEXT: vaddvat.u16 r0, q0
|
||||
; CHECK-NEXT: uxth r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -3899,14 +3866,12 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_zext(<4 x i8> %x, <4 x i8> %y, <4
|
||||
; CHECK-LABEL: add_v4i8_v4i32_acc_zext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i32 q3, #0xff
|
||||
; CHECK-NEXT: vand q2, q2, q3
|
||||
; CHECK-NEXT: vand q1, q1, q3
|
||||
; CHECK-NEXT: vcmp.i32 eq, q2, zr
|
||||
; CHECK-NEXT: vmov.i32 q2, #0x0
|
||||
; CHECK-NEXT: vand q0, q0, q3
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmult.i32 q2, q0, q1
|
||||
; CHECK-NEXT: vaddva.u32 r0, q2
|
||||
; CHECK-NEXT: vmul.i32 q0, q0, q1
|
||||
; CHECK-NEXT: vand q1, q2, q3
|
||||
; CHECK-NEXT: vpt.i32 eq, q1, zr
|
||||
; CHECK-NEXT: vaddvat.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%c = icmp eq <4 x i8> %b, zeroinitializer
|
||||
@ -3922,17 +3887,15 @@ entry:
|
||||
define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b, i32 %a) {
|
||||
; CHECK-LABEL: add_v4i8_v4i32_acc_sext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i32 q3, #0xff
|
||||
; CHECK-NEXT: vmovlb.s8 q1, q1
|
||||
; CHECK-NEXT: vand q2, q2, q3
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vcmp.i32 eq, q2, zr
|
||||
; CHECK-NEXT: vmov.i32 q2, #0x0
|
||||
; CHECK-NEXT: vmovlb.s16 q1, q1
|
||||
; CHECK-NEXT: vmovlb.s16 q0, q0
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmult.i32 q2, q0, q1
|
||||
; CHECK-NEXT: vaddva.u32 r0, q2
|
||||
; CHECK-NEXT: vmul.i32 q0, q0, q1
|
||||
; CHECK-NEXT: vmov.i32 q1, #0xff
|
||||
; CHECK-NEXT: vand q1, q2, q1
|
||||
; CHECK-NEXT: vpt.i32 eq, q1, zr
|
||||
; CHECK-NEXT: vaddvat.u32 r0, q0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%c = icmp eq <4 x i8> %b, zeroinitializer
|
||||
@ -4206,14 +4169,10 @@ entry:
|
||||
define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) {
|
||||
; CHECK-LABEL: add_v8i8_v8i16_acc_zext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovlb.u8 q2, q2
|
||||
; CHECK-NEXT: vmovlb.u8 q1, q1
|
||||
; CHECK-NEXT: vcmp.i16 eq, q2, zr
|
||||
; CHECK-NEXT: vmov.i32 q2, #0x0
|
||||
; CHECK-NEXT: vmovlb.u8 q0, q0
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmult.i16 q2, q0, q1
|
||||
; CHECK-NEXT: vaddva.u16 r0, q2
|
||||
; CHECK-NEXT: vmullb.u8 q0, q0, q1
|
||||
; CHECK-NEXT: vmovlb.u8 q1, q2
|
||||
; CHECK-NEXT: vpt.i16 eq, q1, zr
|
||||
; CHECK-NEXT: vaddvat.u16 r0, q0
|
||||
; CHECK-NEXT: uxth r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -4230,14 +4189,10 @@ entry:
|
||||
define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) {
|
||||
; CHECK-LABEL: add_v8i8_v8i16_acc_sext:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmovlb.u8 q2, q2
|
||||
; CHECK-NEXT: vmovlb.s8 q1, q1
|
||||
; CHECK-NEXT: vcmp.i16 eq, q2, zr
|
||||
; CHECK-NEXT: vmov.i32 q2, #0x0
|
||||
; CHECK-NEXT: vmovlb.s8 q0, q0
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmult.i16 q2, q0, q1
|
||||
; CHECK-NEXT: vaddva.u16 r0, q2
|
||||
; CHECK-NEXT: vmullb.s8 q0, q0, q1
|
||||
; CHECK-NEXT: vmovlb.u8 q1, q2
|
||||
; CHECK-NEXT: vpt.i16 eq, q1, zr
|
||||
; CHECK-NEXT: vaddvat.u16 r0, q0
|
||||
; CHECK-NEXT: sxth r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -4254,10 +4209,9 @@ entry:
|
||||
define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i8 %a) {
|
||||
; CHECK-LABEL: add_v16i8_v16i8_acc:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vmov.i32 q3, #0x0
|
||||
; CHECK-NEXT: vmul.i8 q0, q0, q1
|
||||
; CHECK-NEXT: vpt.i8 eq, q2, zr
|
||||
; CHECK-NEXT: vmult.i8 q3, q0, q1
|
||||
; CHECK-NEXT: vaddva.u8 r0, q3
|
||||
; CHECK-NEXT: vaddvat.u8 r0, q0
|
||||
; CHECK-NEXT: uxtb r0, r0
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user