mirror of
https://github.com/RPCS3/llvm-mirror.git
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Store default libgcc routine names and allow them to be redefined by target.
llvm-svn: 33105
This commit is contained in:
Evan Cheng
parent
8229bc7c80
commit
032a597692
@ -38,6 +38,93 @@ namespace llvm {
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class MachineBasicBlock;
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class MachineInstr;
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namespace RTLIB {
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/// RTLIB::Libcall enum - This enum defines all of the runtime library calls
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/// the backend can emit.
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///
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enum Libcall {
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// Integer
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SHL_I32,
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SHL_I64,
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SRL_I32,
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SRL_I64,
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SRA_I32,
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SRA_I64,
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MUL_I32,
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MUL_I64,
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SDIV_I32,
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SDIV_I64,
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UDIV_I32,
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UDIV_I64,
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SREM_I32,
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SREM_I64,
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UREM_I32,
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UREM_I64,
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NEG_I32,
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NEG_I64,
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// FLOATING POINT
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ADD_F32,
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ADD_F64,
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SUB_F32,
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SUB_F64,
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MUL_F32,
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MUL_F64,
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DIV_F32,
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DIV_F64,
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REM_F32,
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REM_F64,
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NEG_F32,
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NEG_F64,
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POWI_F32,
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POWI_F64,
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SQRT_F32,
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SQRT_F64,
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SIN_F32,
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SIN_F64,
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COS_F32,
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COS_F64,
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// CONVERSION
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FPEXT_F32_F64,
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FPROUND_F64_F32,
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FPTOSINT_F32_I32,
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FPTOSINT_F32_I64,
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FPTOSINT_F64_I32,
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FPTOSINT_F64_I64,
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FPTOUINT_F32_I32,
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FPTOUINT_F32_I64,
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FPTOUINT_F64_I32,
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FPTOUINT_F64_I64,
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SINTTOFP_I32_F32,
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SINTTOFP_I32_F64,
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SINTTOFP_I64_F32,
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SINTTOFP_I64_F64,
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UINTTOFP_I32_F32,
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UINTTOFP_I32_F64,
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UINTTOFP_I64_F32,
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UINTTOFP_I64_F64,
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// COMPARISON
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OEQ_F32,
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OEQ_F64,
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UNE_F32,
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UNE_F64,
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OGE_F32,
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OGE_F64,
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OLT_F32,
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OLT_F64,
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OLE_F32,
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OLE_F64,
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OGT_F32,
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OGT_F64,
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UO_F32,
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UO_F64,
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UNKNOWN_LIBCALL
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};
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}
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//===----------------------------------------------------------------------===//
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/// TargetLowering - This class defines information used to lower LLVM code to
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/// legal SelectionDAG operators that the target instruction selector can accept
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@ -857,6 +944,22 @@ public:
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std::vector<SDNode*>* Created) const;
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//===--------------------------------------------------------------------===//
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// Runtime Library hooks
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//
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/// setLibcallName - Rename the default libcall routine name for the specified
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/// libcall.
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void setLibcallName(RTLIB::Libcall Call, std::string Name) {
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LibcallRoutineNames[Call] = Name;
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}
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/// getLibcallName - Get the libcall routine name for the specified libcall.
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///
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const char *getLibcallName(RTLIB::Libcall Call) const {
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return LibcallRoutineNames[Call].c_str();
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}
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protected:
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/// addLegalAddressScale - Add a integer (> 1) value which can be used as
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/// scale in the target addressing mode. Note: the ordering matters so the
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@ -990,6 +1093,10 @@ private:
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/// this with getTypeToPromoteTo(..).
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std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
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/// LibcallRoutineNames - Stores the name each libcall.
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///
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std::string LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
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protected:
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/// When lowering %llvm.memset this field specifies the maximum number of
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/// store operations that may be substituted for the call to memset. Targets
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@ -2284,11 +2284,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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default: assert(0 && "Do not know how to expand this integer BinOp!");
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case ISD::UDIV:
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case ISD::SDIV:
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const char *FnName = Node->getOpcode() == ISD::UDIV
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? "__udivsi3" : "__divsi3";
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RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
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? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
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SDOperand Dummy;
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bool isSigned = Node->getOpcode() == ISD::SDIV;
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Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
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};
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break;
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}
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@ -2470,16 +2470,18 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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} else {
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assert(Node->getValueType(0) == MVT::i32 &&
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"Cannot expand this binary operator!");
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const char *FnName = Node->getOpcode() == ISD::UREM
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? "__umodsi3" : "__modsi3";
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RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
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? RTLIB::UREM_I32 : RTLIB::SREM_I32;
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SDOperand Dummy;
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Result = ExpandLibCall(FnName, Node, isSigned, Dummy);
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
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}
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} else {
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// Floating point mod -> fmod libcall.
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const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
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RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
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? RTLIB::REM_F32 : RTLIB::REM_F64;
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SDOperand Dummy;
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Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Dummy);
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}
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break;
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}
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@ -2720,15 +2722,22 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::FSIN:
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case ISD::FCOS: {
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MVT::ValueType VT = Node->getValueType(0);
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const char *FnName = 0;
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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switch(Node->getOpcode()) {
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case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
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case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
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case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
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case ISD::FSQRT:
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LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
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break;
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case ISD::FSIN:
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LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
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break;
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case ISD::FCOS:
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LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
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break;
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default: assert(0 && "Unreachable!");
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}
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SDOperand Dummy;
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Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Dummy);
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break;
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}
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}
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@ -2737,10 +2746,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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break;
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case ISD::FPOWI: {
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// We always lower FPOWI into a libcall. No target support it yet.
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const char *FnName = Node->getValueType(0) == MVT::f32
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? "__powisf2" : "__powidf2";
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RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
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? RTLIB::POWI_F32 : RTLIB::POWI_F64;
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SDOperand Dummy;
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Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Dummy);
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break;
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}
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case ISD::BIT_CONVERT:
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@ -2909,24 +2919,29 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case Expand: {
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// Convert f32 / f64 to i32 / i64.
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MVT::ValueType VT = Op.getValueType();
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const char *FnName = 0;
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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switch (Node->getOpcode()) {
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case ISD::FP_TO_SINT:
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if (Node->getOperand(0).getValueType() == MVT::f32)
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FnName = (VT == MVT::i32) ? "__fixsfsi" : "__fixsfdi";
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LC = (VT == MVT::i32)
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? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
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else
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FnName = (VT == MVT::i32) ? "__fixdfsi" : "__fixdfdi";
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LC = (VT == MVT::i32)
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? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
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break;
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case ISD::FP_TO_UINT:
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if (Node->getOperand(0).getValueType() == MVT::f32)
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FnName = (VT == MVT::i32) ? "__fixunssfsi" : "__fixunssfdi";
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LC = (VT == MVT::i32)
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? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
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else
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FnName = (VT == MVT::i32) ? "__fixunsdfsi" : "__fixunsdfdi";
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LC = (VT == MVT::i32)
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? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
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break;
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default: assert(0 && "Unreachable!");
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}
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SDOperand Dummy;
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Result = ExpandLibCall(FnName, Node, false/*sign irrelevant*/, Dummy);
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Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
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false/*sign irrelevant*/, Dummy);
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break;
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}
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case Promote:
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@ -3575,87 +3590,87 @@ void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
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MVT::ValueType VT = LHS.getValueType();
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if (VT == MVT::f32 || VT == MVT::f64) {
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// Expand into one or more soft-fp libcall(s).
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const char *FnName1 = NULL, *FnName2 = NULL;
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RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
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ISD::CondCode CC1, CC2 = ISD::SETCC_INVALID;
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switch (cast<CondCodeSDNode>(CC)->get()) {
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case ISD::SETEQ:
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case ISD::SETOEQ:
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FnName1 = (VT == MVT::f32) ? "__eqsf2" : "__eqdf2";
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LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
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CC1 = ISD::SETEQ;
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break;
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case ISD::SETNE:
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case ISD::SETUNE:
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FnName1 = (VT == MVT::f32) ? "__nesf2" : "__nedf2";
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LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
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CC1 = ISD::SETNE;
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break;
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case ISD::SETGE:
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case ISD::SETOGE:
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FnName1 = (VT == MVT::f32) ? "__gesf2" : "__gedf2";
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LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
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CC1 = ISD::SETGE;
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break;
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case ISD::SETLT:
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case ISD::SETOLT:
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FnName1 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
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LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
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CC1 = ISD::SETLT;
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break;
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case ISD::SETLE:
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case ISD::SETOLE:
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FnName1 = (VT == MVT::f32) ? "__lesf2" : "__ledf2";
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LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
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CC1 = ISD::SETLE;
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break;
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case ISD::SETGT:
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case ISD::SETOGT:
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FnName1 = (VT == MVT::f32) ? "__gtsf2" : "__gtdf2";
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LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
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CC1 = ISD::SETGT;
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break;
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case ISD::SETUO:
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case ISD::SETO:
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FnName1 = (VT == MVT::f32) ? "__unordsf2" : "__unorddf2";
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LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
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CC1 = cast<CondCodeSDNode>(CC)->get() == ISD::SETO
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? ISD::SETEQ : ISD::SETNE;
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break;
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default:
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FnName1 = (VT == MVT::f32) ? "__unordsf2" : "__unorddf2";
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LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
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CC1 = ISD::SETNE;
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switch (cast<CondCodeSDNode>(CC)->get()) {
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case ISD::SETONE:
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// SETONE = SETOLT | SETOGT
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FnName1 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
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LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
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CC1 = ISD::SETLT;
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// Fallthrough
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case ISD::SETUGT:
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FnName2 = (VT == MVT::f32) ? "__gtsf2" : "__gtdf2";
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LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
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CC2 = ISD::SETGT;
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break;
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case ISD::SETUGE:
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FnName2 = (VT == MVT::f32) ? "__gesf2" : "__gedf2";
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LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
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CC2 = ISD::SETGE;
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break;
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case ISD::SETULT:
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FnName2 = (VT == MVT::f32) ? "__ltsf2" : "__ltdf2";
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LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
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CC2 = ISD::SETLT;
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break;
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case ISD::SETULE:
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FnName2 = (VT == MVT::f32) ? "__lesf2" : "__ledf2";
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LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
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CC2 = ISD::SETLE;
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break;
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case ISD::SETUEQ:
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FnName2 = (VT == MVT::f32) ? "__eqsf2" : "__eqdf2";
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CC2 = ISD::SETEQ;
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break;
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case ISD::SETUEQ:
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LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
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CC2 = ISD::SETEQ;
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break;
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default: assert(0 && "Unsupported FP setcc!");
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}
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}
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SDOperand Dummy;
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Tmp1 = ExpandLibCall(FnName1,
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Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
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DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
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false /*sign irrelevant*/, Dummy);
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Tmp2 = DAG.getConstant(0, MVT::i32);
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CC = DAG.getCondCode(CC1);
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if (FnName2) {
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if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
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Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
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LHS = ExpandLibCall(FnName2,
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LHS = ExpandLibCall(TLI.getLibcallName(LC2),
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DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
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false /*sign irrelevant*/, Dummy);
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Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
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@ -4202,17 +4217,18 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
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ExpandOp(Source, SrcLo, SrcHi);
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Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
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const char *FnName = 0;
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RTLIB::Libcall LC;
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if (DestTy == MVT::f32)
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FnName = "__floatdisf";
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LC = RTLIB::SINTTOFP_I64_F32;
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else {
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assert(DestTy == MVT::f64 && "Unknown fp value type!");
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FnName = "__floatdidf";
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LC = RTLIB::SINTTOFP_I64_F64;
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}
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Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
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SDOperand UnusedHiPart;
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return ExpandLibCall(FnName, Source.Val, isSigned, UnusedHiPart);
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return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
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UnusedHiPart);
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}
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/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
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@ -4845,7 +4861,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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// These operators cannot be expanded directly, emit them as calls to
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// library functions.
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_SINT: {
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if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
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SDOperand Op;
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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@ -4864,13 +4880,17 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
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}
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}
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|
||||
RTLIB::Libcall LC;
|
||||
if (Node->getOperand(0).getValueType() == MVT::f32)
|
||||
Lo = ExpandLibCall("__fixsfdi", Node, false/*sign irrelevant*/, Hi);
|
||||
LC = RTLIB::FPTOSINT_F32_I64;
|
||||
else
|
||||
Lo = ExpandLibCall("__fixdfdi", Node, false/*sign irrelevant*/, Hi);
|
||||
LC = RTLIB::FPTOSINT_F64_I64;
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
|
||||
false/*sign irrelevant*/, Hi);
|
||||
break;
|
||||
}
|
||||
|
||||
case ISD::FP_TO_UINT:
|
||||
case ISD::FP_TO_UINT: {
|
||||
if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
|
||||
SDOperand Op;
|
||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||
@ -4888,11 +4908,15 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
}
|
||||
}
|
||||
|
||||
RTLIB::Libcall LC;
|
||||
if (Node->getOperand(0).getValueType() == MVT::f32)
|
||||
Lo = ExpandLibCall("__fixunssfdi", Node, false/*sign irrelevant*/, Hi);
|
||||
LC = RTLIB::FPTOUINT_F32_I64;
|
||||
else
|
||||
Lo = ExpandLibCall("__fixunsdfdi", Node, false/*sign irrelevant*/, Hi);
|
||||
LC = RTLIB::FPTOUINT_F64_I64;
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
|
||||
false/*sign irrelevant*/, Hi);
|
||||
break;
|
||||
}
|
||||
|
||||
case ISD::SHL: {
|
||||
// If the target wants custom lowering, do so.
|
||||
@ -4940,7 +4964,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
}
|
||||
|
||||
// Otherwise, emit a libcall.
|
||||
Lo = ExpandLibCall("__ashldi3", Node, false/*left shift=unsigned*/, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
|
||||
false/*left shift=unsigned*/, Hi);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -4972,7 +4997,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
}
|
||||
|
||||
// Otherwise, emit a libcall.
|
||||
Lo = ExpandLibCall("__ashrdi3", Node, true/*ashr is signed*/, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
|
||||
true/*ashr is signed*/, Hi);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -5004,7 +5030,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
}
|
||||
|
||||
// Otherwise, emit a libcall.
|
||||
Lo = ExpandLibCall("__lshrdi3", Node, false/*lshr is unsigned*/, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
|
||||
false/*lshr is unsigned*/, Hi);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -5091,47 +5118,66 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
}
|
||||
}
|
||||
|
||||
Lo = ExpandLibCall("__muldi3" , Node, false/*sign irrelevant*/, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
|
||||
false/*sign irrelevant*/, Hi);
|
||||
break;
|
||||
}
|
||||
case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, true, Hi); break;
|
||||
case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, false, Hi); break;
|
||||
case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, true, Hi); break;
|
||||
case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, false, Hi); break;
|
||||
case ISD::SDIV:
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
|
||||
break;
|
||||
case ISD::UDIV:
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
|
||||
break;
|
||||
case ISD::SREM:
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
|
||||
break;
|
||||
case ISD::UREM:
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
|
||||
break;
|
||||
|
||||
case ISD::FADD:
|
||||
Lo = ExpandLibCall(((VT == MVT::f32) ? "__addsf3" : "__adddf3"), Node,
|
||||
false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
|
||||
? RTLIB::ADD_F32 : RTLIB::ADD_F64),
|
||||
Node, false, Hi);
|
||||
break;
|
||||
case ISD::FSUB:
|
||||
Lo = ExpandLibCall(((VT == MVT::f32) ? "__subsf3" : "__subdf3"), Node,
|
||||
false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
|
||||
? RTLIB::SUB_F32 : RTLIB::SUB_F64),
|
||||
Node, false, Hi);
|
||||
break;
|
||||
case ISD::FMUL:
|
||||
Lo = ExpandLibCall(((VT == MVT::f32) ? "__mulsf3" : "__muldf3"), Node,
|
||||
false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
|
||||
? RTLIB::MUL_F32 : RTLIB::MUL_F64),
|
||||
Node, false, Hi);
|
||||
break;
|
||||
case ISD::FDIV:
|
||||
Lo = ExpandLibCall(((VT == MVT::f32) ? "__divsf3" : "__divdf3"), Node,
|
||||
false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
|
||||
? RTLIB::DIV_F32 : RTLIB::DIV_F64),
|
||||
Node, false, Hi);
|
||||
break;
|
||||
case ISD::FP_EXTEND:
|
||||
Lo = ExpandLibCall("__extendsfdf2", Node, false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
|
||||
break;
|
||||
case ISD::FP_ROUND:
|
||||
Lo = ExpandLibCall("__truncdfsf2", Node, false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
|
||||
break;
|
||||
case ISD::FSQRT:
|
||||
case ISD::FSIN:
|
||||
case ISD::FCOS: {
|
||||
const char *FnName = 0;
|
||||
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
|
||||
switch(Node->getOpcode()) {
|
||||
case ISD::FSQRT: FnName = (VT == MVT::f32) ? "sqrtf" : "sqrt"; break;
|
||||
case ISD::FSIN: FnName = (VT == MVT::f32) ? "sinf" : "sin"; break;
|
||||
case ISD::FCOS: FnName = (VT == MVT::f32) ? "cosf" : "cos"; break;
|
||||
case ISD::FSQRT:
|
||||
LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
|
||||
break;
|
||||
case ISD::FSIN:
|
||||
LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
|
||||
break;
|
||||
case ISD::FCOS:
|
||||
LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
|
||||
break;
|
||||
default: assert(0 && "Unreachable!");
|
||||
}
|
||||
Lo = ExpandLibCall(FnName, Node, false, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
|
||||
break;
|
||||
}
|
||||
case ISD::FABS: {
|
||||
@ -5166,17 +5212,17 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
case ISD::UINT_TO_FP: {
|
||||
bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
|
||||
MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
|
||||
const char *FnName = 0;
|
||||
RTLIB::Libcall LC;
|
||||
if (Node->getOperand(0).getValueType() == MVT::i64) {
|
||||
if (VT == MVT::f32)
|
||||
FnName = isSigned ? "__floatdisf" : "__floatundisf";
|
||||
LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
|
||||
else
|
||||
FnName = isSigned ? "__floatdidf" : "__floatundidf";
|
||||
LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
|
||||
} else {
|
||||
if (VT == MVT::f32)
|
||||
FnName = isSigned ? "__floatsisf" : "__floatunsisf";
|
||||
LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
|
||||
else
|
||||
FnName = isSigned ? "__floatsidf" : "__floatunsidf";
|
||||
LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
|
||||
}
|
||||
|
||||
// Promote the operand if needed.
|
||||
@ -5188,7 +5234,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
: DAG.getZeroExtendInReg(Tmp, SrcVT);
|
||||
Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
|
||||
}
|
||||
Lo = ExpandLibCall(FnName, Node, isSigned, Hi);
|
||||
Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -21,6 +21,81 @@
|
||||
#include "llvm/Support/MathExtras.h"
|
||||
using namespace llvm;
|
||||
|
||||
/// InitLibcallNames - Set default libcall names.
|
||||
///
|
||||
static void InitLibcallNames(std::string *Names) {
|
||||
Names[RTLIB::SHL_I32] = "__ashlsi3";
|
||||
Names[RTLIB::SHL_I64] = "__ashldi3";
|
||||
Names[RTLIB::SRL_I32] = "__lshrsi3";
|
||||
Names[RTLIB::SRL_I64] = "__lshrdi3";
|
||||
Names[RTLIB::SRA_I32] = "__ashrsi3";
|
||||
Names[RTLIB::SRA_I64] = "__ashrdi3";
|
||||
Names[RTLIB::MUL_I32] = "__mulsi3";
|
||||
Names[RTLIB::MUL_I64] = "__muldi3";
|
||||
Names[RTLIB::SDIV_I32] = "__divsi3";
|
||||
Names[RTLIB::SDIV_I64] = "__divdi3";
|
||||
Names[RTLIB::UDIV_I32] = "__udivsi3";
|
||||
Names[RTLIB::UDIV_I64] = "__udivdi3";
|
||||
Names[RTLIB::SREM_I32] = "__modsi3";
|
||||
Names[RTLIB::SREM_I64] = "__moddi3";
|
||||
Names[RTLIB::UREM_I32] = "__umodsi3";
|
||||
Names[RTLIB::UREM_I64] = "__umoddi3";
|
||||
Names[RTLIB::NEG_I32] = "__negsi2";
|
||||
Names[RTLIB::NEG_I64] = "__negdi2";
|
||||
Names[RTLIB::ADD_F32] = "__addsf3";
|
||||
Names[RTLIB::ADD_F64] = "__adddf3";
|
||||
Names[RTLIB::SUB_F32] = "__subsf3";
|
||||
Names[RTLIB::SUB_F64] = "__subdf3";
|
||||
Names[RTLIB::MUL_F32] = "__mulsf3";
|
||||
Names[RTLIB::MUL_F64] = "__muldf3";
|
||||
Names[RTLIB::DIV_F32] = "__divsf3";
|
||||
Names[RTLIB::DIV_F64] = "__divdf3";
|
||||
Names[RTLIB::REM_F32] = "fmodf";
|
||||
Names[RTLIB::REM_F64] = "fmod";
|
||||
Names[RTLIB::NEG_F32] = "__negsf2";
|
||||
Names[RTLIB::NEG_F64] = "__negdf2";
|
||||
Names[RTLIB::POWI_F32] = "__powisf2";
|
||||
Names[RTLIB::POWI_F64] = "__powidf2";
|
||||
Names[RTLIB::SQRT_F32] = "sqrtf";
|
||||
Names[RTLIB::SQRT_F64] = "sqrt";
|
||||
Names[RTLIB::SIN_F32] = "sinf";
|
||||
Names[RTLIB::SIN_F64] = "sin";
|
||||
Names[RTLIB::COS_F32] = "cosf";
|
||||
Names[RTLIB::COS_F64] = "cos";
|
||||
Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
|
||||
Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
|
||||
Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
|
||||
Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
|
||||
Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
|
||||
Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
|
||||
Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
|
||||
Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
|
||||
Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
|
||||
Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
|
||||
Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
|
||||
Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
|
||||
Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
|
||||
Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
|
||||
Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
|
||||
Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
|
||||
Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
|
||||
Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
|
||||
Names[RTLIB::OEQ_F32] = "__eqsf2";
|
||||
Names[RTLIB::OEQ_F64] = "__eqdf2";
|
||||
Names[RTLIB::UNE_F32] = "__nesf2";
|
||||
Names[RTLIB::UNE_F64] = "__nedf2";
|
||||
Names[RTLIB::OGE_F32] = "__gesf2";
|
||||
Names[RTLIB::OGE_F64] = "__gedf2";
|
||||
Names[RTLIB::OLT_F32] = "__ltsf2";
|
||||
Names[RTLIB::OLT_F64] = "__ltdf2";
|
||||
Names[RTLIB::OLE_F32] = "__lesf2";
|
||||
Names[RTLIB::OLE_F64] = "__ledf2";
|
||||
Names[RTLIB::OGT_F32] = "__gtsf2";
|
||||
Names[RTLIB::OGT_F64] = "__gtdf2";
|
||||
Names[RTLIB::UO_F32] = "__unordsf2";
|
||||
Names[RTLIB::UO_F64] = "__unorddf2";
|
||||
}
|
||||
|
||||
TargetLowering::TargetLowering(TargetMachine &tm)
|
||||
: TM(tm), TD(TM.getTargetData()) {
|
||||
assert(ISD::BUILTIN_OP_END <= 156 &&
|
||||
@ -55,6 +130,8 @@ TargetLowering::TargetLowering(TargetMachine &tm)
|
||||
SchedPreferenceInfo = SchedulingForLatency;
|
||||
JumpBufSize = 0;
|
||||
JumpBufAlignment = 0;
|
||||
|
||||
InitLibcallNames(LibcallRoutineNames);
|
||||
}
|
||||
|
||||
TargetLowering::~TargetLowering() {}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user