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[MirNamer][Canonicalizer]: Perform instruction semantic based renaming
https://reviews.llvm.org/D70210 Previously: Due to sensitivity of the algorithm with gaps, and extra instructions, when diffing, often we see naming being off by a few. Makes the diff unreadable even for tests with 7 and 8 instructions respectively. Naming can change depending on candidates (and order of picking candidates). Suddenly if there's one extra instruction somewhere, the entire subtree would be named completely differently. No consistent naming of similar instructions which occur in different functions. If we try to do something like count the frequency distribution of various differences across suite, then the above sensitivity issues are going to result in poor results. Instead: Name instruction based on semantics of the instruction (hash of the opcode and operands). Essentially for a given instruction that occurs in any module/function it'll be named similarly (ie semantic). This has some nice properties Can easily look at many instructions and just check the hash and if they're named similarly, then it's the same instruction. Makes it very easy to spot the same instruction both multiple times, as well as across many functions (useful for frequency distribution). Independent of traversal/candidates/depth of graph. No need to keep track of last index/gaps/skip count etc. No off by few issues with diffs. I've tried the old vs new implementation in files ranging from 30 to 700 instructions. In both cases with the old algorithm, diffs are a sea of red, where as for the semantic version, in both cases, the diffs line up beautifully. Simplified implementation of the main loop (simple iteration) , no keep track of what's visited and not. Handle collision just by incrementing a counter. Roughly bb[N]_hash_[CollisionCount]. Additionally with the new implementation, we can probably avoid doing the hoisting of instructions to various places, as they'll likely be named the same resulting in differences only based on collision (ie regardless of whether the instruction is hoisted or not/close to use or not, it'll be named the same hash which should result in use of the instruction be identical with the only change being the collision count) which is very easy to spot visually.
This commit is contained in:
Aditya Nandakumar
parent
c1ff3621ab
commit
032b2a6c3d
@ -375,7 +375,7 @@ static bool doDefKillClear(MachineBasicBlock *MBB) {
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static bool runOnBasicBlock(MachineBasicBlock *MBB,
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std::vector<StringRef> &bbNames,
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unsigned &basicBlockNum, NamedVRegCursor &NVC) {
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unsigned &basicBlockNum, VRegRenamer &Renamer) {
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if (CanonicalizeBasicBlockNumber != ~0U) {
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if (CanonicalizeBasicBlockNumber != basicBlockNum++)
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@ -398,8 +398,6 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
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});
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bool Changed = false;
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MachineFunction &MF = *MBB->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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bbNames.push_back(MBB->getName());
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LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
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@ -414,31 +412,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
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Changed |= rescheduleCanonically(IdempotentInstCount, MBB);
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LLVM_DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
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Changed |= NVC.renameVRegs(MBB);
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// Here we renumber the def vregs for the idempotent instructions from the top
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// of the MachineBasicBlock so that they are named in the order that we sorted
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// them alphabetically. Eventually we wont need SkipVRegs because we will use
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// named vregs instead.
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if (IdempotentInstCount)
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NVC.skipVRegs();
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auto MII = MBB->begin();
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for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
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MachineInstr &MI = *MII++;
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Changed = true;
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Register vRegToRename = MI.getOperand(0).getReg();
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auto Rename = NVC.createVirtualRegister(vRegToRename);
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std::vector<MachineOperand *> RenameMOs;
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for (auto &MO : MRI.reg_operands(vRegToRename)) {
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RenameMOs.push_back(&MO);
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}
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for (auto *MO : RenameMOs) {
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MO->setReg(Rename);
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}
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}
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Changed |= Renamer.renameVRegs(MBB);
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Changed |= doDefKillClear(MBB);
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@ -478,9 +452,9 @@ bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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NamedVRegCursor NVC(MRI);
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VRegRenamer Renamer(MRI);
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for (auto MBB : RPOList)
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Changed |= runOnBasicBlock(MBB, BBNames, BBNum, NVC);
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Changed |= runOnBasicBlock(MBB, BBNames, BBNum, Renamer);
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return Changed;
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}
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@ -55,11 +55,11 @@ public:
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if (MF.empty())
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return Changed;
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NamedVRegCursor NVC(MF.getRegInfo());
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VRegRenamer Renamer(MF.getRegInfo());
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ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
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for (auto &MBB : RPOT)
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Changed |= NVC.renameVRegs(MBB);
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Changed |= Renamer.renameVRegs(MBB);
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return Changed;
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}
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@ -13,226 +13,14 @@ using namespace llvm;
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#define DEBUG_TYPE "mir-vregnamer-utils"
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namespace {
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// TypedVReg and VRType are used to tell the renamer what to do at points in a
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// sequence of values to be renamed. A TypedVReg can either contain
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// an actual VReg, a FrameIndex, or it could just be a barrier for the next
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// candidate (side-effecting instruction). This tells the renamer to increment
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// to the next vreg name, or to skip modulo some skip-gap value.
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enum VRType { RSE_Reg = 0, RSE_FrameIndex, RSE_NewCandidate };
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class TypedVReg {
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VRType Type;
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Register Reg;
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public:
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TypedVReg(Register Reg) : Type(RSE_Reg), Reg(Reg) {}
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TypedVReg(VRType Type) : Type(Type), Reg(~0U) {
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assert(Type != RSE_Reg && "Expected a non-Register Type.");
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}
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bool isReg() const { return Type == RSE_Reg; }
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bool isFrameIndex() const { return Type == RSE_FrameIndex; }
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bool isCandidate() const { return Type == RSE_NewCandidate; }
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VRType getType() const { return Type; }
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Register getReg() const {
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assert(this->isReg() && "Expected a virtual or physical Register.");
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return Reg;
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}
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};
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/// Here we find our candidates. What makes an interesting candidate?
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/// A candidate for a canonicalization tree root is normally any kind of
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/// instruction that causes side effects such as a store to memory or a copy to
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/// a physical register or a return instruction. We use these as an expression
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/// tree root that we walk in order to build a canonical walk which should
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/// result in canonical vreg renaming.
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std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
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std::vector<MachineInstr *> Candidates;
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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for (auto II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
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MachineInstr *MI = &*II;
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bool DoesMISideEffect = false;
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if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
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const Register Dst = MI->getOperand(0).getReg();
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DoesMISideEffect |= !Register::isVirtualRegister(Dst);
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for (auto UI = MRI.use_begin(Dst); UI != MRI.use_end(); ++UI) {
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if (DoesMISideEffect)
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break;
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DoesMISideEffect |= (UI->getParent()->getParent() != MI->getParent());
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}
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}
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if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect)
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continue;
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LLVM_DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
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Candidates.push_back(MI);
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}
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return Candidates;
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}
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void doCandidateWalk(std::vector<TypedVReg> &VRegs,
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std::queue<TypedVReg> &RegQueue,
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std::vector<MachineInstr *> &VisitedMIs,
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const MachineBasicBlock *MBB) {
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const MachineFunction &MF = *MBB->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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while (!RegQueue.empty()) {
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auto TReg = RegQueue.front();
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RegQueue.pop();
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if (TReg.isFrameIndex()) {
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LLVM_DEBUG(dbgs() << "Popping frame index.\n";);
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VRegs.push_back(TypedVReg(RSE_FrameIndex));
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continue;
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}
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assert(TReg.isReg() && "Expected vreg or physreg.");
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Register Reg = TReg.getReg();
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if (Register::isVirtualRegister(Reg)) {
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LLVM_DEBUG({
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dbgs() << "Popping vreg ";
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MRI.def_begin(Reg)->dump();
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dbgs() << "\n";
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});
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if (!llvm::any_of(VRegs, [&](const TypedVReg &TR) {
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return TR.isReg() && TR.getReg() == Reg;
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})) {
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VRegs.push_back(TypedVReg(Reg));
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}
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} else {
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LLVM_DEBUG(dbgs() << "Popping physreg.\n";);
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VRegs.push_back(TypedVReg(Reg));
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continue;
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}
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for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) {
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MachineInstr *Def = RI->getParent();
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if (Def->getParent() != MBB)
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continue;
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if (llvm::any_of(VisitedMIs,
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[&](const MachineInstr *VMI) { return Def == VMI; })) {
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break;
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}
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LLVM_DEBUG({
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dbgs() << "\n========================\n";
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dbgs() << "Visited MI: ";
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Def->dump();
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dbgs() << "BB Name: " << Def->getParent()->getName() << "\n";
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dbgs() << "\n========================\n";
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});
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VisitedMIs.push_back(Def);
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for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
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MachineOperand &MO = Def->getOperand(I);
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if (MO.isFI()) {
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LLVM_DEBUG(dbgs() << "Pushing frame index.\n";);
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RegQueue.push(TypedVReg(RSE_FrameIndex));
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}
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if (!MO.isReg())
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continue;
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RegQueue.push(TypedVReg(MO.getReg()));
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}
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}
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}
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}
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std::map<unsigned, unsigned>
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getVRegRenameMap(const std::vector<TypedVReg> &VRegs,
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const std::vector<Register> &renamedInOtherBB,
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MachineRegisterInfo &MRI, NamedVRegCursor &NVC) {
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std::map<unsigned, unsigned> VRegRenameMap;
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bool FirstCandidate = true;
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for (auto &vreg : VRegs) {
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if (vreg.isFrameIndex()) {
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// We skip one vreg for any frame index because there is a good chance
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// (especially when comparing SelectionDAG to GlobalISel generated MIR)
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// that in the other file we are just getting an incoming vreg that comes
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// from a copy from a frame index. So it's safe to skip by one.
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unsigned LastRenameReg = NVC.incrementVirtualVReg();
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(void)LastRenameReg;
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LLVM_DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
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continue;
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} else if (vreg.isCandidate()) {
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// After the first candidate, for every subsequent candidate, we skip mod
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// 10 registers so that the candidates are more likely to start at the
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// same vreg number making it more likely that the canonical walk from the
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// candidate insruction. We don't need to skip from the first candidate of
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// the BasicBlock because we already skip ahead several vregs for each BB.
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unsigned LastRenameReg = NVC.getVirtualVReg();
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if (FirstCandidate)
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NVC.incrementVirtualVReg(LastRenameReg % 10);
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FirstCandidate = false;
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continue;
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} else if (!Register::isVirtualRegister(vreg.getReg())) {
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unsigned LastRenameReg = NVC.incrementVirtualVReg();
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(void)LastRenameReg;
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LLVM_DEBUG({
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dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n";
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});
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continue;
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}
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auto Reg = vreg.getReg();
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if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) {
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LLVM_DEBUG(dbgs() << "Vreg " << Reg
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<< " already renamed in other BB.\n";);
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continue;
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}
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auto Rename = NVC.createVirtualRegister(Reg);
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if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
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LLVM_DEBUG(dbgs() << "Mapping vreg ";);
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if (MRI.reg_begin(Reg) != MRI.reg_end()) {
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LLVM_DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
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} else {
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LLVM_DEBUG(dbgs() << Reg;);
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}
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LLVM_DEBUG(dbgs() << " to ";);
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if (MRI.reg_begin(Rename) != MRI.reg_end()) {
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LLVM_DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
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} else {
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LLVM_DEBUG(dbgs() << Rename;);
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}
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LLVM_DEBUG(dbgs() << "\n";);
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VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
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}
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}
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return VRegRenameMap;
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}
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bool doVRegRenaming(std::vector<Register> &renamedInOtherBB,
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const std::map<unsigned, unsigned> &VRegRenameMap,
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MachineRegisterInfo &MRI) {
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bool VRegRenamer::doVRegRenaming(
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const std::map<unsigned, unsigned> &VRegRenameMap) {
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bool Changed = false;
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for (auto I = VRegRenameMap.begin(), E = VRegRenameMap.end(); I != E; ++I) {
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auto VReg = I->first;
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auto Rename = I->second;
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renamedInOtherBB.push_back(Rename);
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std::vector<MachineOperand *> RenameMOs;
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for (auto &MO : MRI.reg_operands(VReg)) {
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RenameMOs.push_back(&MO);
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@ -250,99 +38,108 @@ bool doVRegRenaming(std::vector<Register> &renamedInOtherBB,
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return Changed;
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}
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bool renameVRegs(MachineBasicBlock *MBB,
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std::vector<Register> &renamedInOtherBB,
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NamedVRegCursor &NVC) {
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bool Changed = false;
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MachineFunction &MF = *MBB->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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std::map<unsigned, unsigned>
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VRegRenamer::getVRegRenameMap(const std::vector<NamedVReg> &VRegs) {
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std::map<unsigned, unsigned> VRegRenameMap;
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std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
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std::vector<MachineInstr *> VisitedMIs;
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llvm::copy(Candidates, std::back_inserter(VisitedMIs));
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std::map<std::string, unsigned> VRegNameCollisionMap;
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std::vector<TypedVReg> VRegs;
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for (auto candidate : Candidates) {
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VRegs.push_back(TypedVReg(RSE_NewCandidate));
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std::queue<TypedVReg> RegQueue;
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// Here we walk the vreg operands of a non-root node along our walk.
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// The root nodes are the original candidates (stores normally).
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// These are normally not the root nodes (except for the case of copies to
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// physical registers).
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for (unsigned i = 1; i < candidate->getNumOperands(); i++) {
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if (candidate->mayStore() || candidate->isBranch())
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break;
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MachineOperand &MO = candidate->getOperand(i);
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if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
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continue;
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LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
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RegQueue.push(TypedVReg(MO.getReg()));
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auto GetUniqueVRegName =
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[&VRegNameCollisionMap](const NamedVReg &Reg) -> std::string {
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auto It = VRegNameCollisionMap.find(Reg.getName());
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unsigned Counter = 0;
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if (It != VRegNameCollisionMap.end()) {
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Counter = It->second;
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}
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++Counter;
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VRegNameCollisionMap[Reg.getName()] = Counter;
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return Reg.getName() + "__" + std::to_string(Counter);
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};
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// Here we walk the root candidates. We start from the 0th operand because
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// the root is normally a store to a vreg.
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for (unsigned i = 0; i < candidate->getNumOperands(); i++) {
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for (auto &Vreg : VRegs) {
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auto Reg = Vreg.getReg();
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assert(Register::isVirtualRegister(Reg) &&
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"Expecting Virtual Registers Only");
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auto NewNameForReg = GetUniqueVRegName(Vreg);
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auto Rename = createVirtualRegisterWithName(Reg, NewNameForReg);
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if (!candidate->mayStore() && !candidate->isBranch())
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break;
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VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
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}
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return VRegRenameMap;
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}
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MachineOperand &MO = candidate->getOperand(i);
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// TODO: Do we want to only add vregs here?
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if (!MO.isReg() && !MO.isFI())
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continue;
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LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
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RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
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: TypedVReg(RSE_FrameIndex));
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std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
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std::string S;
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raw_string_ostream OS(S);
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auto HashOperand = [this](const MachineOperand &MO) -> unsigned {
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if (MO.isImm())
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return MO.getImm();
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if (MO.isTargetIndex())
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return MO.getOffset() | (MO.getTargetFlags() << 16);
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if (MO.isReg()) {
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return Register::isVirtualRegister(MO.getReg())
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? MRI.getVRegDef(MO.getReg())->getOpcode()
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: (unsigned)MO.getReg();
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}
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// We could explicitly handle all the types of the MachineOperand,
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// here but we can just return a common number until we find a
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// compelling test case where this is bad. The only side effect here
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// is contributing to a hash collission but there's enough information
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// (Opcodes,other registers etc) that this will likely not be a problem.
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return 0;
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};
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SmallVector<unsigned, 16> MIOperands;
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MIOperands.push_back(MI.getOpcode());
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for (auto &Op : MI.uses()) {
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MIOperands.push_back(HashOperand(Op));
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}
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auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());
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return std::to_string(HashMI).substr(0, 5);
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}
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|
||||
doCandidateWalk(VRegs, RegQueue, VisitedMIs, MBB);
|
||||
unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
|
||||
return createVirtualRegisterWithName(
|
||||
VReg, getInstructionOpcodeHash(*MRI.getVRegDef(VReg)));
|
||||
}
|
||||
|
||||
bool VRegRenamer::renameInstsInMBB(MachineBasicBlock *MBB) {
|
||||
std::vector<NamedVReg> VRegs;
|
||||
std::string Prefix = "bb" + std::to_string(getCurrentBBNumber()) + "_";
|
||||
for (auto &MII : *MBB) {
|
||||
MachineInstr &Candidate = MII;
|
||||
// Don't rename stores/branches.
|
||||
if (Candidate.mayStore() || Candidate.isBranch())
|
||||
continue;
|
||||
if (!Candidate.getNumOperands())
|
||||
continue;
|
||||
// Look for instructions that define VRegs in operand 0.
|
||||
MachineOperand &MO = Candidate.getOperand(0);
|
||||
// Avoid non regs, instructions defining physical regs.
|
||||
if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
|
||||
continue;
|
||||
VRegs.push_back(
|
||||
NamedVReg(MO.getReg(), Prefix + getInstructionOpcodeHash(Candidate)));
|
||||
}
|
||||
|
||||
// If we have populated no vregs to rename then bail.
|
||||
// The rest of this function does the vreg remaping.
|
||||
if (VRegs.size() == 0)
|
||||
return Changed;
|
||||
return false;
|
||||
|
||||
auto VRegRenameMap = getVRegRenameMap(VRegs, renamedInOtherBB, MRI, NVC);
|
||||
Changed |= doVRegRenaming(renamedInOtherBB, VRegRenameMap, MRI);
|
||||
return Changed;
|
||||
}
|
||||
} // anonymous namespace
|
||||
|
||||
void NamedVRegCursor::skipVRegs() {
|
||||
unsigned VRegGapIndex = 1;
|
||||
if (!virtualVRegNumber) {
|
||||
VRegGapIndex = 0;
|
||||
virtualVRegNumber = MRI.createIncompleteVirtualRegister();
|
||||
}
|
||||
const unsigned VR_GAP = (++VRegGapIndex * SkipGapSize);
|
||||
|
||||
unsigned I = virtualVRegNumber;
|
||||
const unsigned E = (((I + VR_GAP) / VR_GAP) + 1) * VR_GAP;
|
||||
|
||||
virtualVRegNumber = E;
|
||||
auto VRegRenameMap = getVRegRenameMap(VRegs);
|
||||
return doVRegRenaming(VRegRenameMap);
|
||||
}
|
||||
|
||||
unsigned NamedVRegCursor::createVirtualRegister(unsigned VReg) {
|
||||
if (!virtualVRegNumber)
|
||||
skipVRegs();
|
||||
std::string S;
|
||||
raw_string_ostream OS(S);
|
||||
OS << "namedVReg" << (virtualVRegNumber & ~0x80000000);
|
||||
OS.flush();
|
||||
virtualVRegNumber++;
|
||||
bool VRegRenamer::renameVRegs(MachineBasicBlock *MBB, unsigned BBNum) {
|
||||
CurrentBBNumber = BBNum;
|
||||
return renameInstsInMBB(MBB);
|
||||
}
|
||||
|
||||
unsigned VRegRenamer::createVirtualRegisterWithName(unsigned VReg,
|
||||
const std::string &Name) {
|
||||
std::string Temp(Name);
|
||||
std::transform(Temp.begin(), Temp.end(), Temp.begin(), ::tolower);
|
||||
if (auto RC = MRI.getRegClassOrNull(VReg))
|
||||
return MRI.createVirtualRegister(RC, OS.str());
|
||||
return MRI.createGenericVirtualRegister(MRI.getType(VReg), OS.str());
|
||||
}
|
||||
|
||||
bool NamedVRegCursor::renameVRegs(MachineBasicBlock *MBB) {
|
||||
return ::renameVRegs(MBB, RenamedInOtherBB, *this);
|
||||
return MRI.createVirtualRegister(RC, Temp);
|
||||
return MRI.createGenericVirtualRegister(MRI.getType(VReg), Name);
|
||||
}
|
||||
|
||||
@ -25,65 +25,68 @@
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
#include "llvm/Support/raw_ostream.h"
|
||||
|
||||
#include <queue>
|
||||
|
||||
namespace llvm {
|
||||
/// VRegRenamer - This class is used for renaming vregs in a machine basic
|
||||
/// block according to semantics of the instruction.
|
||||
class VRegRenamer {
|
||||
class NamedVReg {
|
||||
Register Reg;
|
||||
std::string Name;
|
||||
|
||||
public:
|
||||
NamedVReg(Register Reg, std::string Name = "") : Reg(Reg), Name(Name) {}
|
||||
NamedVReg(std::string Name = "") : Reg(~0U), Name(Name) {}
|
||||
|
||||
const std::string &getName() const { return Name; }
|
||||
|
||||
Register getReg() const { return Reg; }
|
||||
};
|
||||
|
||||
/// NamedVRegCursor - The cursor is an object that keeps track of what the next
|
||||
/// vreg name should be. It does book keeping to determine when to skip the
|
||||
/// index value and by how much, or if the next vreg name should be an increment
|
||||
/// from the previous.
|
||||
class NamedVRegCursor {
|
||||
MachineRegisterInfo &MRI;
|
||||
|
||||
/// virtualVRegNumber - Book keeping of the last vreg position.
|
||||
unsigned virtualVRegNumber;
|
||||
unsigned CurrentBBNumber = 0;
|
||||
|
||||
/// SkipGapSize - Used to calculate a modulo amount to skip by after every
|
||||
/// sequence of instructions starting from a given side-effecting
|
||||
/// MachineInstruction for a given MachineBasicBlock. The general idea is that
|
||||
/// for a given program compiled with two different opt pipelines, there
|
||||
/// shouldn't be greater than SkipGapSize difference in how many vregs are in
|
||||
/// play between the two and for every def-use graph of vregs we rename we
|
||||
/// will round up to the next SkipGapSize'th number so that we have a high
|
||||
/// change of landing on the same name for two given matching side-effects
|
||||
/// for the two compilation outcomes.
|
||||
const unsigned SkipGapSize;
|
||||
/// Given an Instruction, construct a hash of the operands
|
||||
/// of the instructions along with the opcode.
|
||||
/// When dealing with virtual registers, just hash the opcode of
|
||||
/// the instruction defining that vreg.
|
||||
/// Handle immediates, registers (physical and virtual) explicitly,
|
||||
/// and return a common value for the other cases.
|
||||
/// Instruction will be named in the following scheme
|
||||
/// bb<block_no>_hash_<collission_count>.
|
||||
std::string getInstructionOpcodeHash(MachineInstr &MI);
|
||||
|
||||
/// RenamedInOtherBB - VRegs that we already renamed: ie breadcrumbs.
|
||||
std::vector<Register> RenamedInOtherBB;
|
||||
/// For all the VRegs that are candidates for renaming,
|
||||
/// return a mapping from old vregs to new vregs with names.
|
||||
std::map<unsigned, unsigned>
|
||||
getVRegRenameMap(const std::vector<NamedVReg> &VRegs);
|
||||
|
||||
/// Perform replacing of registers based on the <old,new> vreg map.
|
||||
bool doVRegRenaming(const std::map<unsigned, unsigned> &VRegRenameMap);
|
||||
|
||||
public:
|
||||
NamedVRegCursor() = delete;
|
||||
/// 1000 for the SkipGapSize was a good heuristic at the time of the writing
|
||||
/// of the MIRCanonicalizerPass. Adjust as needed.
|
||||
NamedVRegCursor(MachineRegisterInfo &MRI, unsigned SkipGapSize = 1000)
|
||||
: MRI(MRI), virtualVRegNumber(0), SkipGapSize(SkipGapSize) {}
|
||||
|
||||
/// SkipGapSize - Skips modulo a gap value of indices. Indices are used to
|
||||
/// produce the next vreg name.
|
||||
void skipVRegs();
|
||||
|
||||
unsigned getVirtualVReg() const { return virtualVRegNumber; }
|
||||
|
||||
/// incrementVirtualVReg - This increments an index value that us used to
|
||||
/// create a new vreg name. This is not a Register.
|
||||
unsigned incrementVirtualVReg(unsigned incr = 1) {
|
||||
virtualVRegNumber += incr;
|
||||
return virtualVRegNumber;
|
||||
}
|
||||
VRegRenamer() = delete;
|
||||
VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {}
|
||||
|
||||
/// createVirtualRegister - Given an existing vreg, create a named vreg to
|
||||
/// take its place.
|
||||
/// take its place. The name is determined by calling
|
||||
/// getInstructionOpcodeHash.
|
||||
unsigned createVirtualRegister(unsigned VReg);
|
||||
|
||||
/// renameVRegs - For a given MachineBasicBlock, scan for side-effecting
|
||||
/// instructions, walk the def-use from each side-effecting root (in sorted
|
||||
/// root order) and rename the encountered vregs in the def-use graph in a
|
||||
/// canonical ordering. This method maintains book keeping for which vregs
|
||||
/// were already renamed in RenamedInOtherBB.
|
||||
// @return changed
|
||||
bool renameVRegs(MachineBasicBlock *MBB);
|
||||
/// Create a vreg with name and return it.
|
||||
unsigned createVirtualRegisterWithName(unsigned VReg,
|
||||
const std::string &Name);
|
||||
/// Linearly traverse the MachineBasicBlock and rename each instruction's
|
||||
/// vreg definition based on the semantics of the instruction.
|
||||
/// Names are as follows bb<BBNum>_hash_[0-9]+
|
||||
bool renameInstsInMBB(MachineBasicBlock *MBB);
|
||||
|
||||
/// Same as the above, but sets a BBNum depending on BB traversal that
|
||||
/// will be used as prefix for the vreg names.
|
||||
bool renameVRegs(MachineBasicBlock *MBB, unsigned BBNum = 0);
|
||||
|
||||
unsigned getCurrentBBNumber() const { return CurrentBBNumber; }
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
@ -39,8 +39,8 @@ body: |
|
||||
|
||||
%42:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
|
||||
|
||||
;CHECK: %namedVReg1352:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
|
||||
;CHECK-NEXT: $w0 = COPY %namedVReg1352
|
||||
;CHECK: %bb0_11909__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
|
||||
;CHECK-NEXT: $w0 = COPY %bb0_11909__1
|
||||
;CHECK-NEXT: RET_ReallyLR implicit $w0
|
||||
|
||||
%vreg1234:gpr32 = COPY %42
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
# RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s
|
||||
# These Idempotent instructions are sorted alphabetically (based on after the '=')
|
||||
# CHECK: %namedVReg4352:gpr64 = MOVi64imm 4617315517961601024
|
||||
# CHECK-NEXT: %namedVReg4353:gpr32 = MOVi32imm 408
|
||||
# CHECK-NEXT: %namedVReg4354:gpr32 = MOVi32imm 408
|
||||
# CHECK-NEXT: %namedVReg4355:gpr64all = IMPLICIT_DEF
|
||||
# CHECK-NEXT: %namedVReg4356:fpr64 = FMOVDi 20
|
||||
# CHECK-NEXT: %namedVReg4357:fpr64 = FMOVDi 112
|
||||
# CHECK: %bb0_17169__1:gpr64 = MOVi64imm 4617315517961601024
|
||||
# CHECK-NEXT: %bb0_42274__1:gpr32 = MOVi32imm 408
|
||||
# CHECK-NEXT: %bb0_42274__2:gpr32 = MOVi32imm 408
|
||||
# CHECK-NEXT: %bb0_18275__1:gpr64all = IMPLICIT_DEF
|
||||
# CHECK-NEXT: %bb0_13880__1:fpr64 = FMOVDi 20
|
||||
# CHECK-NEXT: %bb0_21467__1:fpr64 = FMOVDi 112
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
@ -5,10 +5,10 @@ name: foo
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
;CHECK: bb
|
||||
;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0
|
||||
;CHECK-NEXT: %namedVReg1352:_(<4 x s32>) = COPY $q0
|
||||
;CHECK-NEXT: G_STORE %namedVReg1352(<4 x s32>), %namedVReg1353
|
||||
;CHECK-LABEL: bb.0
|
||||
;CHECK-NEXT: %bb0_12265__1:_(p0) = COPY $d0
|
||||
;CHECK-NEXT: %bb0_18308__1:_(<4 x s32>) = COPY $q0
|
||||
;CHECK-NEXT: G_STORE %bb0_18308__1(<4 x s32>), %bb0_12265__1(p0) :: (store 16)
|
||||
|
||||
liveins: $q0, $d0
|
||||
%1:fpr(p0) = COPY $d0
|
||||
@ -25,20 +25,20 @@ stack:
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
;CHECK: bb
|
||||
;CHECK-NEXT: %namedVReg1370:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %namedVReg1371:gpr32 = MOVi32imm 1
|
||||
;CHECK-NEXT: %namedVReg1372:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %namedVReg1373:gpr32 = MOVi32imm 2
|
||||
;CHECK-NEXT: %namedVReg1359:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %namedVReg1360:gpr32 = MOVi32imm 3
|
||||
;CHECK-NEXT: %namedVReg1365:gpr32 = nsw ADDWrr
|
||||
;CHECK-NEXT: %namedVReg1361:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %namedVReg1366:gpr32 = nsw ADDWrr
|
||||
;CHECK-NEXT: %namedVReg1362:gpr32 = MOVi32imm 4
|
||||
;CHECK-NEXT: %namedVReg1355:gpr32 = nsw ADDWrr
|
||||
;CHECK-NEXT: %namedVReg1363:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %namedVReg1364:gpr32 = MOVi32imm 5
|
||||
;CHECK-LABEL: bb.0
|
||||
;CHECK-NEXT: %bb0_11909__1:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %bb0_17251__1:gpr32 = MOVi32imm 1
|
||||
;CHECK-NEXT: %bb0_11909__2:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %bb0_44296__1:gpr32 = MOVi32imm 2
|
||||
;CHECK-NEXT: %bb0_11909__3:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %bb0_10150__1:gpr32 = MOVi32imm 3
|
||||
;CHECK-NEXT: %bb0_18184__1:gpr32 = nsw ADDWrr
|
||||
;CHECK-NEXT: %bb0_11909__4:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %bb0_18184__2:gpr32 = nsw ADDWrr
|
||||
;CHECK-NEXT: %bb0_56622__1:gpr32 = MOVi32imm 4
|
||||
;CHECK-NEXT: %bb0_18184__3:gpr32 = nsw ADDWrr
|
||||
;CHECK-NEXT: %bb0_11909__5:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %bb0_74788__1:gpr32 = MOVi32imm 5
|
||||
|
||||
%0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
|
||||
%1:gpr32 = MOVi32imm 1
|
||||
@ -73,12 +73,12 @@ body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1, $d0, $d1
|
||||
|
||||
;CHECK: bb
|
||||
;CHECK-NEXT: %namedVReg1355:gpr32 = LDRWui
|
||||
;CHECK-NEXT: %namedVReg1354:gpr32 = COPY %namedVReg1355
|
||||
;CHECK-NEXT: %namedVReg1353:gpr32 = COPY %namedVReg1354
|
||||
;CHECK-NEXT: %namedVReg1352:gpr32 = COPY %namedVReg1353
|
||||
;CHECK-NEXT: $w0 = COPY %namedVReg1352
|
||||
;CHECK-LABEL: bb.0:
|
||||
;CHECK-NEXT: %bb0_11909__1:gpr32 = LDRWui %stack.0, 0
|
||||
;CHECK-NEXT: %bb0_31408__1:gpr32 = COPY %bb0_11909__1
|
||||
;CHECK-NEXT: %bb0_14282__1:gpr32 = COPY %bb0_31408__1
|
||||
;CHECK-NEXT: %bb0_14282__2:gpr32 = COPY %bb0_14282__1
|
||||
;CHECK-NEXT: $w0 = COPY %bb0_14282__2
|
||||
|
||||
%0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
|
||||
%1:gpr32 = COPY %0
|
||||
|
||||
@ -1,18 +1,26 @@
|
||||
# RUN: llc -o - -march=amdgcn -run-pass mir-canonicalizer -x mir %s | FileCheck %s
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -o - -march=amdgcn -run-pass mir-canonicalizer %s | FileCheck %s
|
||||
|
||||
# CHECK: %namedVReg4354:vgpr_32 = COPY $vgpr0
|
||||
# CHECK: %namedVReg1352:vgpr_32 = COPY %namedVReg4353
|
||||
# CHECK-NEXT: %namedVReg1358:vgpr_32 = COPY %namedVReg1361
|
||||
# CHECK-NEXT: %namedVReg1359:vgpr_32 = COPY %namedVReg1362
|
||||
# CHECK-NEXT: %namedVReg1353:vreg_64 = REG_SEQUENCE %namedVReg4354, %subreg.sub0, %namedVReg1352, %subreg.sub1
|
||||
# CHECK-NEXT: %namedVReg1354:sgpr_128 = REG_SEQUENCE %namedVReg4354, %subreg.sub0, %namedVReg1352, %subreg.sub1, %namedVReg1358, %subreg.sub2, %namedVReg1359, %subreg.sub3
|
||||
# This tests for the itereator invalidation fix (reviews.llvm.org/D62713)
|
||||
# CHECK-NEXT: BUFFER_STORE_DWORD_ADDR64 %namedVReg1352, %namedVReg1353, %namedVReg1354, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
...
|
||||
---
|
||||
name: foo
|
||||
body: |
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: foo
|
||||
; CHECK: %bb0_43693__1:sreg_32_xm0 = S_MOV_B32 61440
|
||||
; CHECK: %bb0_13829__1:sreg_32_xm0 = S_MOV_B32 0
|
||||
; CHECK: %bb0_14481__1:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: %bb0_18142__1:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
; CHECK: %bb0_16462__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_18142__1, 9, 0, 0
|
||||
; CHECK: %bb0_89962__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_18142__1, 11, 0, 0
|
||||
; CHECK: %bb0_10035__1:vgpr_32 = COPY %bb0_13829__1
|
||||
; CHECK: %bb0_18361__1:vgpr_32 = COPY %bb0_16462__1
|
||||
; CHECK: %bb0_18361__2:vgpr_32 = COPY %bb0_89962__1
|
||||
; CHECK: %bb0_16181__1:vreg_64 = REG_SEQUENCE %bb0_14481__1, %subreg.sub0, %bb0_10035__1, %subreg.sub1
|
||||
; CHECK: %bb0_71315__1:sgpr_128 = REG_SEQUENCE %bb0_14481__1, %subreg.sub0, %bb0_10035__1, %subreg.sub1, %bb0_18361__1, %subreg.sub2, %bb0_18361__2, %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_10035__1, %bb0_16181__1, %bb0_71315__1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; CHECK: S_ENDPGM 0
|
||||
%10:sreg_32_xm0 = S_MOV_B32 61440
|
||||
%11:sreg_32_xm0 = S_MOV_B32 0
|
||||
%3:vgpr_32 = COPY $vgpr0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user