mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
[mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions
Differential Revision: http://reviews.llvm.org/D14174 llvm-svn: 253332
This commit is contained in:
Zlatko Buljan
parent
73a323728d
commit
032cc29f2d
@ -128,3 +128,16 @@ class POOL32A_2RSA4OP6_FMT<string opstr, bits<6> op> : MMDSPInst<opstr> {
|
||||
let Inst{11-6} = op;
|
||||
let Inst{5-0} = 0b111100;
|
||||
}
|
||||
|
||||
class POOL32A_1RIMM5AC_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> imm;
|
||||
bits<2> ac;
|
||||
|
||||
let Inst{31-26} = 0b000000;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = imm;
|
||||
let Inst{15-14} = ac;
|
||||
let Inst{13-6} = funct;
|
||||
let Inst{5-0} = 0b111100;
|
||||
}
|
||||
|
||||
@ -90,6 +90,18 @@ class SUBU_QB_MM_ENC : POOL32A_3R_FMT<"subu.qb", 0b01011001101>;
|
||||
class SUBU_S_QB_MM_ENC : POOL32A_3R_FMT<"subu_s.qb", 0b11011001101>;
|
||||
class SUBUH_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh.qb", 0b01101001101>;
|
||||
class SUBUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh_r.qb", 0b11101001101>;
|
||||
class EXTP_MM_ENC : POOL32A_1RIMM5AC_FMT<"extp", 0b10011001>;
|
||||
class EXTPDP_MM_ENC : POOL32A_1RIMM5AC_FMT<"extpdp", 0b11011001>;
|
||||
class EXTPDPV_MM_ENC : POOL32A_2RAC_FMT<"extpdpv", 0b11100010>;
|
||||
class EXTPV_MM_ENC : POOL32A_2RAC_FMT<"extpv", 0b10100010>;
|
||||
class EXTR_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr.w", 0b00111001>;
|
||||
class EXTR_R_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_r.w", 0b01111001>;
|
||||
class EXTR_RS_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_rs.w", 0b10111001>;
|
||||
class EXTR_S_H_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_s.h", 0b11111001>;
|
||||
class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>;
|
||||
class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>;
|
||||
class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>;
|
||||
class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>;
|
||||
|
||||
// Instruction desc.
|
||||
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
|
||||
@ -197,6 +209,57 @@ class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
|
||||
class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
|
||||
"shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>;
|
||||
|
||||
class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$rs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $rs");
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm");
|
||||
InstrItinClass Itinerary = itin;
|
||||
}
|
||||
class EXTP_MM_DESC
|
||||
: EXT_MM_1R_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
|
||||
Uses<[DSPPos]>, Defs<[DSPEFI]>;
|
||||
class EXTPDP_MM_DESC
|
||||
: EXT_MM_1R_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
|
||||
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
|
||||
class EXTPDPV_MM_DESC
|
||||
: EXT_MM_2R_DESC_BASE<"extpdpv", MipsEXTPDP, NoItinerary>,
|
||||
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
|
||||
class EXTPV_MM_DESC
|
||||
: EXT_MM_2R_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
|
||||
Uses<[DSPPos]>, Defs<[DSPEFI]>;
|
||||
class EXTR_W_MM_DESC
|
||||
: EXT_MM_1R_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTR_R_W_MM_DESC
|
||||
: EXT_MM_1R_DESC_BASE<"extr_r.w", MipsEXTR_R_W, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTR_RS_W_MM_DESC
|
||||
: EXT_MM_1R_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTR_S_H_MM_DESC
|
||||
: EXT_MM_1R_DESC_BASE<"extr_s.h", MipsEXTR_S_H, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTRV_W_MM_DESC
|
||||
: EXT_MM_2R_DESC_BASE<"extrv.w", MipsEXTR_W, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTRV_R_W_MM_DESC
|
||||
: EXT_MM_2R_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTRV_RS_W_MM_DESC
|
||||
: EXT_MM_2R_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
class EXTRV_S_H_MM_DESC
|
||||
: EXT_MM_2R_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, NoItinerary>,
|
||||
Defs<[DSPOutFlag23]>;
|
||||
|
||||
// Instruction defs.
|
||||
// microMIPS DSP Rev 1
|
||||
def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
|
||||
@ -252,6 +315,18 @@ def SUBQ_S_PH_MM : DspMMRel, SUBQ_S_PH_MM_ENC, SUBQ_S_PH_DESC;
|
||||
def SUBQ_S_W_MM : DspMMRel, SUBQ_S_W_MM_ENC, SUBQ_S_W_DESC;
|
||||
def SUBU_QB_MM : DspMMRel, SUBU_QB_MM_ENC, SUBU_QB_DESC;
|
||||
def SUBU_S_QB_MM : DspMMRel, SUBU_S_QB_MM_ENC, SUBU_S_QB_DESC;
|
||||
def EXTP_MM : DspMMRel, EXTP_MM_ENC, EXTP_MM_DESC;
|
||||
def EXTPDP_MM : DspMMRel, EXTPDP_MM_ENC, EXTPDP_MM_DESC;
|
||||
def EXTPDPV_MM : DspMMRel, EXTPDPV_MM_ENC, EXTPDPV_MM_DESC;
|
||||
def EXTPV_MM : DspMMRel, EXTPV_MM_ENC, EXTPV_MM_DESC;
|
||||
def EXTR_W_MM : DspMMRel, EXTR_W_MM_ENC, EXTR_W_MM_DESC;
|
||||
def EXTR_R_W_MM : DspMMRel, EXTR_R_W_MM_ENC, EXTR_R_W_MM_DESC;
|
||||
def EXTR_RS_W_MM : DspMMRel, EXTR_RS_W_MM_ENC, EXTR_RS_W_MM_DESC;
|
||||
def EXTR_S_H_MM : DspMMRel, EXTR_S_H_MM_ENC, EXTR_S_H_MM_DESC;
|
||||
def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC;
|
||||
def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC;
|
||||
def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC;
|
||||
def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC;
|
||||
// microMIPS DSP Rev 2
|
||||
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
|
||||
ISA_DSPR2;
|
||||
|
||||
@ -388,6 +388,7 @@ class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
|
||||
InstrItinClass Itinerary = itin;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
@ -396,6 +397,7 @@ class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
|
||||
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
|
||||
InstrItinClass Itinerary = itin;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
|
||||
@ -1183,18 +1185,18 @@ def LHX : LHX_ENC, LHX_DESC;
|
||||
def LBUX : LBUX_ENC, LBUX_DESC;
|
||||
def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
|
||||
def INSV : DspMMRel, INSV_ENC, INSV_DESC;
|
||||
def EXTP : EXTP_ENC, EXTP_DESC;
|
||||
def EXTPV : EXTPV_ENC, EXTPV_DESC;
|
||||
def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
|
||||
def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
|
||||
def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
|
||||
def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
|
||||
def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
|
||||
def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
|
||||
def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
|
||||
def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
|
||||
def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
|
||||
def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
|
||||
def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
|
||||
def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
|
||||
def EXTPDP : DspMMRel, EXTPDP_ENC, EXTPDP_DESC;
|
||||
def EXTPDPV : DspMMRel, EXTPDPV_ENC, EXTPDPV_DESC;
|
||||
def EXTR_W : DspMMRel, EXTR_W_ENC, EXTR_W_DESC;
|
||||
def EXTRV_W : DspMMRel, EXTRV_W_ENC, EXTRV_W_DESC;
|
||||
def EXTR_R_W : DspMMRel, EXTR_R_W_ENC, EXTR_R_W_DESC;
|
||||
def EXTRV_R_W : DspMMRel, EXTRV_R_W_ENC, EXTRV_R_W_DESC;
|
||||
def EXTR_RS_W : DspMMRel, EXTR_RS_W_ENC, EXTR_RS_W_DESC;
|
||||
def EXTRV_RS_W : DspMMRel, EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
|
||||
def EXTR_S_H : DspMMRel, EXTR_S_H_ENC, EXTR_S_H_DESC;
|
||||
def EXTRV_S_H : DspMMRel, EXTRV_S_H_ENC, EXTRV_S_H_DESC;
|
||||
def SHILO : SHILO_ENC, SHILO_DESC;
|
||||
def SHILOV : SHILOV_ENC, SHILOV_DESC;
|
||||
def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
|
||||
|
||||
@ -13,6 +13,18 @@
|
||||
0x00 0x64 0x92 0xbc # CHECK: dpaq_sa.l.w $ac2, $4, $3
|
||||
0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4
|
||||
0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21
|
||||
0x00 0x06 0x66 0x7c # CHECK: extp $zero, $ac1, 6
|
||||
0x00 0x42 0x76 0x7c # CHECK: extpdp $2, $ac1, 2
|
||||
0x00 0x88 0xb8 0xbc # CHECK: extpdpv $4, $ac2, $8
|
||||
0x01 0xe7 0xe8 0xbc # CHECK: extpv $15, $ac3, $7
|
||||
0x03 0x7f 0xce 0x7c # CHECK: extr.w $27, $ac3, 31
|
||||
0x01 0x98 0x1e 0x7c # CHECK: extr_r.w $12, $ac0, 24
|
||||
0x03 0x69 0xee 0x7c # CHECK: extr_rs.w $27, $ac3, 9
|
||||
0x00 0x61 0xbe 0x7c # CHECK: extr_s.h $3, $ac2, 1
|
||||
0x00 0xa6 0x0e 0xbc # CHECK: extrv.w $5, $ac0, $6
|
||||
0x01 0x43 0x1e 0xbc # CHECK: extrv_r.w $10, $ac0, $3
|
||||
0x01 0xf4 0x6e 0xbc # CHECK: extrv_rs.w $15, $ac1, $20
|
||||
0x01 0x10 0xbe 0xbc # CHECK: extrv_s.h $8, $ac2, $16
|
||||
0x00 0x64 0x41 0x3c # CHECK: insv $3, $4
|
||||
0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7
|
||||
0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9
|
||||
|
||||
@ -26,6 +26,18 @@
|
||||
0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4
|
||||
0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21
|
||||
0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1
|
||||
0x00 0x06 0x66 0x7c # CHECK: extp $zero, $ac1, 6
|
||||
0x00 0x42 0x76 0x7c # CHECK: extpdp $2, $ac1, 2
|
||||
0x00 0x88 0xb8 0xbc # CHECK: extpdpv $4, $ac2, $8
|
||||
0x01 0xe7 0xe8 0xbc # CHECK: extpv $15, $ac3, $7
|
||||
0x03 0x7f 0xce 0x7c # CHECK: extr.w $27, $ac3, 31
|
||||
0x01 0x98 0x1e 0x7c # CHECK: extr_r.w $12, $ac0, 24
|
||||
0x03 0x69 0xee 0x7c # CHECK: extr_rs.w $27, $ac3, 9
|
||||
0x00 0x61 0xbe 0x7c # CHECK: extr_s.h $3, $ac2, 1
|
||||
0x00 0xa6 0x0e 0xbc # CHECK: extrv.w $5, $ac0, $6
|
||||
0x01 0x43 0x1e 0xbc # CHECK: extrv_r.w $10, $ac0, $3
|
||||
0x01 0xf4 0x6e 0xbc # CHECK: extrv_rs.w $15, $ac1, $20
|
||||
0x01 0x10 0xbe 0xbc # CHECK: extrv_s.h $8, $ac2, $16
|
||||
0x00 0x64 0x41 0x3c # CHECK: insv $3, $4
|
||||
0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7
|
||||
0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9
|
||||
|
||||
@ -14,6 +14,18 @@
|
||||
dpaq_sa.l.w $ac2, $4, $3 # CHECK: dpaq_sa.l.w $ac2, $4, $3 # encoding: [0x00,0x64,0x92,0xbc]
|
||||
dpau.h.qbl $ac1, $3, $4 # CHECK: dpau.h.qbl $ac1, $3, $4 # encoding: [0x00,0x83,0x60,0xbc]
|
||||
dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
|
||||
extp $zero, $ac1, 6 # CHECK: extp $zero, $ac1, 6 # encoding: [0x00,0x06,0x66,0x7c]
|
||||
extpdp $2, $ac1, 2 # CHECK: extpdp $2, $ac1, 2 # encoding: [0x00,0x42,0x76,0x7c]
|
||||
extpdpv $4, $ac2, $8 # CHECK: extpdpv $4, $ac2, $8 # encoding: [0x00,0x88,0xb8,0xbc]
|
||||
extpv $15, $ac3, $7 # CHECK: extpv $15, $ac3, $7 # encoding: [0x01,0xe7,0xe8,0xbc]
|
||||
extr.w $27, $ac3, 31 # CHECK: extr.w $27, $ac3, 31 # encoding: [0x03,0x7f,0xce,0x7c]
|
||||
extr_r.w $12, $ac0, 24 # CHECK: extr_r.w $12, $ac0, 24 # encoding: [0x01,0x98,0x1e,0x7c]
|
||||
extr_rs.w $27, $ac3, 9 # CHECK: extr_rs.w $27, $ac3, 9 # encoding: [0x03,0x69,0xee,0x7c]
|
||||
extr_s.h $3, $ac2, 1 # CHECK: extr_s.h $3, $ac2, 1 # encoding: [0x00,0x61,0xbe,0x7c]
|
||||
extrv.w $5, $ac0, $6 # CHECK: extrv.w $5, $ac0, $6 # encoding: [0x00,0xa6,0x0e,0xbc]
|
||||
extrv_r.w $10, $ac0, $3 # CHECK: extrv_r.w $10, $ac0, $3 # encoding: [0x01,0x43,0x1e,0xbc]
|
||||
extrv_rs.w $15, $ac1, $20 # CHECK: extrv_rs.w $15, $ac1, $20 # encoding: [0x01,0xf4,0x6e,0xbc]
|
||||
extrv_s.h $8, $ac2, $16 # CHECK: extrv_s.h $8, $ac2, $16 # encoding: [0x01,0x10,0xbe,0xbc]
|
||||
insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c]
|
||||
madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc]
|
||||
maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc]
|
||||
|
||||
@ -27,6 +27,18 @@
|
||||
dpau.h.qbl $ac1, $3, $4 # CHECK: dpau.h.qbl $ac1, $3, $4 # encoding: [0x00,0x83,0x60,0xbc]
|
||||
dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
|
||||
dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc]
|
||||
extp $zero, $ac1, 6 # CHECK: extp $zero, $ac1, 6 # encoding: [0x00,0x06,0x66,0x7c]
|
||||
extpdp $2, $ac1, 2 # CHECK: extpdp $2, $ac1, 2 # encoding: [0x00,0x42,0x76,0x7c]
|
||||
extpdpv $4, $ac2, $8 # CHECK: extpdpv $4, $ac2, $8 # encoding: [0x00,0x88,0xb8,0xbc]
|
||||
extpv $15, $ac3, $7 # CHECK: extpv $15, $ac3, $7 # encoding: [0x01,0xe7,0xe8,0xbc]
|
||||
extr.w $27, $ac3, 31 # CHECK: extr.w $27, $ac3, 31 # encoding: [0x03,0x7f,0xce,0x7c]
|
||||
extr_r.w $12, $ac0, 24 # CHECK: extr_r.w $12, $ac0, 24 # encoding: [0x01,0x98,0x1e,0x7c]
|
||||
extr_rs.w $27, $ac3, 9 # CHECK: extr_rs.w $27, $ac3, 9 # encoding: [0x03,0x69,0xee,0x7c]
|
||||
extr_s.h $3, $ac2, 1 # CHECK: extr_s.h $3, $ac2, 1 # encoding: [0x00,0x61,0xbe,0x7c]
|
||||
extrv.w $5, $ac0, $6 # CHECK: extrv.w $5, $ac0, $6 # encoding: [0x00,0xa6,0x0e,0xbc]
|
||||
extrv_r.w $10, $ac0, $3 # CHECK: extrv_r.w $10, $ac0, $3 # encoding: [0x01,0x43,0x1e,0xbc]
|
||||
extrv_rs.w $15, $ac1, $20 # CHECK: extrv_rs.w $15, $ac1, $20 # encoding: [0x01,0xf4,0x6e,0xbc]
|
||||
extrv_s.h $8, $ac2, $16 # CHECK: extrv_s.h $8, $ac2, $16 # encoding: [0x01,0x10,0xbe,0xbc]
|
||||
insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c]
|
||||
madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc]
|
||||
maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user