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vector load store with length (left justified) llvm portion

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llvm-svn: 286993
This commit is contained in:
Zaara Syeda 2016-11-15 17:54:19 +00:00
parent 6ee084f4af
commit 032feaa279
3 changed files with 74 additions and 4 deletions
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12
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -741,6 +741,18 @@ def int_ppc_vsx_lxvw4x_be :
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
def int_ppc_vsx_lxvd2x_be :
Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
def int_ppc_vsx_lxvl :
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem,
IntrArgMemOnly]>;
def int_ppc_vsx_lxvll :
Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem,
IntrArgMemOnly]>;
def int_ppc_vsx_stxvl :
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
[IntrArgMemOnly]>;
def int_ppc_vsx_stxvll :
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
[IntrArgMemOnly]>;
// Vector store.
def int_ppc_vsx_stxvw4x :

20
lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -2333,8 +2333,14 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
[(set v2f64:$XT, (load xoaddr:$src))]>;
// Load Vector (Left-justified) with Length
def LXVL : X_XT6_RA5_RB5<31, 269, "lxvl" , vsrc, []>;
def LXVLL : X_XT6_RA5_RB5<31, 301, "lxvll" , vsrc, []>;
def LXVL : XX1Form<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
"lxvl $XT, $src, $rB", IIC_LdStLoad,
[(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>,
UseVSXReg;
def LXVLL : XX1Form<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
"lxvll $XT, $src, $rB", IIC_LdStLoad,
[(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>,
UseVSXReg;
// Load Vector Word & Splat Indexed
def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
@ -2378,8 +2384,14 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
[(store v2f64:$XT, xoaddr:$dst)]>;
// Store Vector (Left-justified) with Length
def STXVL : X_XS6_RA5_RB5<31, 397, "stxvl" , vsrc, []>;
def STXVLL : X_XS6_RA5_RB5<31, 429, "stxvll" , vsrc, []>;
def STXVL : XX1Form<31, 397, (outs), (ins vsrc:$XT, memr:$dst, g8rc:$rB),
"stxvl $XT, $dst, $rB", IIC_LdStLoad,
[(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst, i64:$rB)]>,
UseVSXReg;
def STXVLL : XX1Form<31, 429, (outs), (ins vsrc:$XT, memr:$dst, g8rc:$rB),
"stxvll $XT, $dst, $rB", IIC_LdStLoad,
[(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst, i64:$rB)]>,
UseVSXReg;
} // mayStore
// Patterns for which instructions from ISA 3.0 are a better match

46
test/CodeGen/PowerPC/vsx-p9.ll
View File

@ -342,4 +342,50 @@ entry:
; Function Attrs: nounwind readnone
declare <4 x float>@llvm.ppc.vsx.xvcvhpsp(<8 x i16>)
; Function Attrs: nounwind readnone
define <4 x i32> @testLXVL(i8* %a, i64 %b) {
entry:
%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvl(i8* %a, i64 %b)
ret <4 x i32> %0
; CHECK-LABEL: testLXVL
; CHECK: lxvl 34, 3, 4
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.vsx.lxvl(i8*, i64)
define void @testSTXVL(<4 x i32> %a, i8* %b, i64 %c) {
entry:
tail call void @llvm.ppc.vsx.stxvl(<4 x i32> %a, i8* %b, i64 %c)
ret void
; CHECK-LABEL: testSTXVL
; CHECK: stxvl 34, 5, 6
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare void @llvm.ppc.vsx.stxvl(<4 x i32>, i8*, i64)
; Function Attrs: nounwind readnone
define <4 x i32> @testLXVLL(i8* %a, i64 %b) {
entry:
%0 = tail call <4 x i32> @llvm.ppc.vsx.lxvll(i8* %a, i64 %b)
ret <4 x i32> %0
; CHECK-LABEL: testLXVLL
; CHECK: lxvll 34, 3, 4
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.vsx.lxvll(i8*, i64)
define void @testSTXVLL(<4 x i32> %a, i8* %b, i64 %c) {
entry:
tail call void @llvm.ppc.vsx.stxvll(<4 x i32> %a, i8* %b, i64 %c)
ret void
; CHECK-LABEL: testSTXVLL
; CHECK: stxvll 34, 5, 6
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare void @llvm.ppc.vsx.stxvll(<4 x i32>, i8*, i64)
declare void @sink(...)