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Simplify max/minp[s|d] dagcombine matching
llvm-svn: 140199
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@ -12562,17 +12562,14 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
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// Get the LHS/RHS of the select.
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// Get the LHS/RHS of the select.
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SDValue LHS = N->getOperand(1);
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SDValue LHS = N->getOperand(1);
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SDValue RHS = N->getOperand(2);
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SDValue RHS = N->getOperand(2);
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EVT VT = LHS.getValueType();
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// If we have SSE[12] support, try to form min/max nodes. SSE min/max
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// If we have SSE[12] support, try to form min/max nodes. SSE min/max
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// instructions match the semantics of the common C idiom x<y?x:y but not
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// instructions match the semantics of the common C idiom x<y?x:y but not
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// x<=y?x:y, because of how they handle negative zero (which can be
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// x<=y?x:y, because of how they handle negative zero (which can be
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// ignored in unsafe-math mode).
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// ignored in unsafe-math mode).
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if (Cond.getOpcode() == ISD::SETCC &&
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if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
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((Subtarget->hasXMMInt() &&
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VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
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(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::v4f32 ||
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LHS.getValueType() == MVT::f64 || LHS.getValueType() == MVT::v2f64)) ||
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(Subtarget->hasAVX() &&
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(LHS.getValueType() == MVT::v8f32 || LHS.getValueType() == MVT::v4f64)))) {
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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unsigned Opcode = 0;
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unsigned Opcode = 0;
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