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[SystemZ] Return scalarized costs for vector instructions on older archs.
A cost query for a vector instruction should return a cost even without target vector support, and not trigger an assert. VectorCombine does this with an input containing source code vectors. Review: Ulrich Weigand
This commit is contained in:
Jonas Paulsson
parent
f6d46e3d59
commit
035c4568cc
@ -391,9 +391,57 @@ int SystemZTTIImpl::getArithmeticInstrCost(
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}
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}
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if (Ty->isVectorTy()) {
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assert(ST->hasVector() &&
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"getArithmeticInstrCost() called with vector type.");
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if (!Ty->isVectorTy()) {
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// These FP operations are supported with a dedicated instruction for
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// float, double and fp128 (base implementation assumes float generally
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// costs 2).
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if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
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Opcode == Instruction::FMul || Opcode == Instruction::FDiv)
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return 1;
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// There is no native support for FRem.
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if (Opcode == Instruction::FRem)
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return LIBCALL_COST;
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// Give discount for some combined logical operations if supported.
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if (Args.size() == 2 && ST->hasMiscellaneousExtensions3()) {
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if (Opcode == Instruction::Xor) {
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for (const Value *A : Args) {
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if (const Instruction *I = dyn_cast<Instruction>(A))
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if (I->hasOneUse() &&
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(I->getOpcode() == Instruction::And ||
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I->getOpcode() == Instruction::Or ||
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I->getOpcode() == Instruction::Xor))
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return 0;
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}
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}
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else if (Opcode == Instruction::Or || Opcode == Instruction::And) {
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for (const Value *A : Args) {
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if (const Instruction *I = dyn_cast<Instruction>(A))
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if (I->hasOneUse() && I->getOpcode() == Instruction::Xor)
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return 0;
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}
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}
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}
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// Or requires one instruction, although it has custom handling for i64.
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if (Opcode == Instruction::Or)
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return 1;
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if (Opcode == Instruction::Xor && ScalarBits == 1) {
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if (ST->hasLoadStoreOnCond2())
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return 5; // 2 * (li 0; loc 1); xor
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return 7; // 2 * ipm sequences ; xor ; shift ; compare
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}
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if (DivRemConstPow2)
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return (SignedDivRem ? SDivPow2Cost : 1);
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if (DivRemConst)
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return DivMulSeqCost;
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if (SignedDivRem || UnsignedDivRem)
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return DivInstrCost;
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}
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else if (ST->hasVector()) {
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unsigned VF = Ty->getVectorNumElements();
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unsigned NumVectors = getNumVectorRegs(Ty);
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@ -454,56 +502,6 @@ int SystemZTTIImpl::getArithmeticInstrCost(
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return Cost;
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}
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}
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else { // Scalar:
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// These FP operations are supported with a dedicated instruction for
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// float, double and fp128 (base implementation assumes float generally
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// costs 2).
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if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
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Opcode == Instruction::FMul || Opcode == Instruction::FDiv)
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return 1;
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// There is no native support for FRem.
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if (Opcode == Instruction::FRem)
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return LIBCALL_COST;
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// Give discount for some combined logical operations if supported.
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if (Args.size() == 2 && ST->hasMiscellaneousExtensions3()) {
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if (Opcode == Instruction::Xor) {
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for (const Value *A : Args) {
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if (const Instruction *I = dyn_cast<Instruction>(A))
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if (I->hasOneUse() &&
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(I->getOpcode() == Instruction::And ||
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I->getOpcode() == Instruction::Or ||
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I->getOpcode() == Instruction::Xor))
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return 0;
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}
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}
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else if (Opcode == Instruction::Or || Opcode == Instruction::And) {
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for (const Value *A : Args) {
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if (const Instruction *I = dyn_cast<Instruction>(A))
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if (I->hasOneUse() && I->getOpcode() == Instruction::Xor)
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return 0;
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}
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}
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}
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// Or requires one instruction, although it has custom handling for i64.
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if (Opcode == Instruction::Or)
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return 1;
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if (Opcode == Instruction::Xor && ScalarBits == 1) {
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if (ST->hasLoadStoreOnCond2())
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return 5; // 2 * (li 0; loc 1); xor
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return 7; // 2 * ipm sequences ; xor ; shift ; compare
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}
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if (DivRemConstPow2)
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return (SignedDivRem ? SDivPow2Cost : 1);
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if (DivRemConst)
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return DivMulSeqCost;
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if (SignedDivRem || UnsignedDivRem)
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return DivInstrCost;
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}
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// Fallback to the default implementation.
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
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@ -513,35 +511,36 @@ int SystemZTTIImpl::getArithmeticInstrCost(
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int SystemZTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp) {
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assert (Tp->isVectorTy());
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assert (ST->hasVector() && "getShuffleCost() called.");
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unsigned NumVectors = getNumVectorRegs(Tp);
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if (ST->hasVector()) {
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unsigned NumVectors = getNumVectorRegs(Tp);
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// TODO: Since fp32 is expanded, the shuffle cost should always be 0.
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// TODO: Since fp32 is expanded, the shuffle cost should always be 0.
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// FP128 values are always in scalar registers, so there is no work
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// involved with a shuffle, except for broadcast. In that case register
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// moves are done with a single instruction per element.
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if (Tp->getScalarType()->isFP128Ty())
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return (Kind == TargetTransformInfo::SK_Broadcast ? NumVectors - 1 : 0);
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// FP128 values are always in scalar registers, so there is no work
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// involved with a shuffle, except for broadcast. In that case register
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// moves are done with a single instruction per element.
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if (Tp->getScalarType()->isFP128Ty())
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return (Kind == TargetTransformInfo::SK_Broadcast ? NumVectors - 1 : 0);
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switch (Kind) {
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case TargetTransformInfo::SK_ExtractSubvector:
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// ExtractSubvector Index indicates start offset.
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switch (Kind) {
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case TargetTransformInfo::SK_ExtractSubvector:
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// ExtractSubvector Index indicates start offset.
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// Extracting a subvector from first index is a noop.
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return (Index == 0 ? 0 : NumVectors);
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// Extracting a subvector from first index is a noop.
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return (Index == 0 ? 0 : NumVectors);
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case TargetTransformInfo::SK_Broadcast:
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// Loop vectorizer calls here to figure out the extra cost of
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// broadcasting a loaded value to all elements of a vector. Since vlrep
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// loads and replicates with a single instruction, adjust the returned
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// value.
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return NumVectors - 1;
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case TargetTransformInfo::SK_Broadcast:
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// Loop vectorizer calls here to figure out the extra cost of
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// broadcasting a loaded value to all elements of a vector. Since vlrep
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// loads and replicates with a single instruction, adjust the returned
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// value.
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return NumVectors - 1;
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default:
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default:
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// SystemZ supports single instruction permutation / replication.
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return NumVectors;
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// SystemZ supports single instruction permutation / replication.
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return NumVectors;
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}
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}
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return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
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@ -672,8 +671,36 @@ int SystemZTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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unsigned DstScalarBits = Dst->getScalarSizeInBits();
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unsigned SrcScalarBits = Src->getScalarSizeInBits();
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if (Src->isVectorTy()) {
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assert (ST->hasVector() && "getCastInstrCost() called with vector type.");
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if (!Src->isVectorTy()) {
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assert (!Dst->isVectorTy());
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if (Opcode == Instruction::SIToFP || Opcode == Instruction::UIToFP) {
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if (SrcScalarBits >= 32 ||
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(I != nullptr && isa<LoadInst>(I->getOperand(0))))
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return 1;
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return SrcScalarBits > 1 ? 2 /*i8/i16 extend*/ : 5 /*branch seq.*/;
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}
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if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
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Src->isIntegerTy(1)) {
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if (ST->hasLoadStoreOnCond2())
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return 2; // li 0; loc 1
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// This should be extension of a compare i1 result, which is done with
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// ipm and a varying sequence of instructions.
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unsigned Cost = 0;
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if (Opcode == Instruction::SExt)
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Cost = (DstScalarBits < 64 ? 3 : 4);
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if (Opcode == Instruction::ZExt)
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Cost = 3;
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Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I) : nullptr);
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if (CmpOpTy != nullptr && CmpOpTy->isFloatingPointTy())
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// If operands of an fp-type was compared, this costs +1.
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Cost++;
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return Cost;
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}
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}
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else if (ST->hasVector()) {
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assert (Dst->isVectorTy());
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unsigned VF = Src->getVectorNumElements();
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unsigned NumDstVectors = getNumVectorRegs(Dst);
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@ -759,35 +786,6 @@ int SystemZTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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return VF + getScalarizationOverhead(Src, false, true);
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}
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}
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else { // Scalar
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assert (!Dst->isVectorTy());
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if (Opcode == Instruction::SIToFP || Opcode == Instruction::UIToFP) {
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if (SrcScalarBits >= 32 ||
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(I != nullptr && isa<LoadInst>(I->getOperand(0))))
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return 1;
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return SrcScalarBits > 1 ? 2 /*i8/i16 extend*/ : 5 /*branch seq.*/;
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}
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if ((Opcode == Instruction::ZExt || Opcode == Instruction::SExt) &&
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Src->isIntegerTy(1)) {
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if (ST->hasLoadStoreOnCond2())
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return 2; // li 0; loc 1
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// This should be extension of a compare i1 result, which is done with
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// ipm and a varying sequence of instructions.
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unsigned Cost = 0;
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if (Opcode == Instruction::SExt)
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Cost = (DstScalarBits < 64 ? 3 : 4);
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if (Opcode == Instruction::ZExt)
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Cost = 3;
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Type *CmpOpTy = ((I != nullptr) ? getCmpOpsType(I) : nullptr);
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if (CmpOpTy != nullptr && CmpOpTy->isFloatingPointTy())
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// If operands of an fp-type was compared, this costs +1.
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Cost++;
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return Cost;
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}
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}
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return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
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}
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@ -806,8 +804,31 @@ static unsigned getOperandsExtensionCost(const Instruction *I) {
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int SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy, const Instruction *I) {
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if (ValTy->isVectorTy()) {
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assert (ST->hasVector() && "getCmpSelInstrCost() called with vector type.");
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if (!ValTy->isVectorTy()) {
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switch (Opcode) {
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case Instruction::ICmp: {
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// A loaded value compared with 0 with multiple users becomes Load and
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// Test. The load is then not foldable, so return 0 cost for the ICmp.
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unsigned ScalarBits = ValTy->getScalarSizeInBits();
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if (I != nullptr && ScalarBits >= 32)
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if (LoadInst *Ld = dyn_cast<LoadInst>(I->getOperand(0)))
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if (const ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
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if (!Ld->hasOneUse() && Ld->getParent() == I->getParent() &&
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C->getZExtValue() == 0)
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return 0;
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unsigned Cost = 1;
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if (ValTy->isIntegerTy() && ValTy->getScalarSizeInBits() <= 16)
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Cost += (I != nullptr ? getOperandsExtensionCost(I) : 2);
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return Cost;
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}
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case Instruction::Select:
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if (ValTy->isFloatingPointTy())
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return 4; // No load on condition for FP - costs a conditional jump.
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return 1; // Load On Condition / Select Register.
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}
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}
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else if (ST->hasVector()) {
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unsigned VF = ValTy->getVectorNumElements();
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// Called with a compare instruction.
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@ -856,30 +877,6 @@ int SystemZTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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return getNumVectorRegs(ValTy) /*vsel*/ + PackCost;
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}
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}
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else { // Scalar
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switch (Opcode) {
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case Instruction::ICmp: {
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// A loaded value compared with 0 with multiple users becomes Load and
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// Test. The load is then not foldable, so return 0 cost for the ICmp.
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unsigned ScalarBits = ValTy->getScalarSizeInBits();
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if (I != nullptr && ScalarBits >= 32)
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if (LoadInst *Ld = dyn_cast<LoadInst>(I->getOperand(0)))
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if (const ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
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if (!Ld->hasOneUse() && Ld->getParent() == I->getParent() &&
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C->getZExtValue() == 0)
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return 0;
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unsigned Cost = 1;
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if (ValTy->isIntegerTy() && ValTy->getScalarSizeInBits() <= 16)
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Cost += (I != nullptr ? getOperandsExtensionCost(I) : 2);
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return Cost;
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}
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case Instruction::Select:
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if (ValTy->isFloatingPointTy())
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return 4; // No load on condition for FP - costs a conditional jump.
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return 1; // Load On Condition / Select Register.
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}
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}
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return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, nullptr);
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}
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13
test/Analysis/CostModel/SystemZ/oldarch-vectors.ll
Normal file
13
test/Analysis/CostModel/SystemZ/oldarch-vectors.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z10
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;
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; Check that some costs can be returned for vector instructions also without
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; vector support.
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define void @fun(<2 x double>* %arg) {
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entry:
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%add = fadd <2 x double> undef, undef
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shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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%conv = fptoui <4 x float> undef to <4 x i32>
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%cmp = icmp eq <2 x i64> undef, undef
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ret void
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}
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