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[SVE] Lower fixed length vector integer ISD::SETCC operations.
Differential Revision: https://reviews.llvm.org/D85831
This commit is contained in:
Paul Walker
parent
aecc53e597
commit
036bc786e9
@ -1106,6 +1106,7 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
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setOperationAction(ISD::LOAD, VT, Custom);
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setOperationAction(ISD::MUL, VT, Custom);
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setOperationAction(ISD::OR, VT, Custom);
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setOperationAction(ISD::SETCC, VT, Custom);
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setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
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setOperationAction(ISD::STORE, VT, Custom);
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@ -9198,6 +9199,9 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
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return LowerToPredicatedOp(Op, DAG, AArch64ISD::SETCC_MERGE_ZERO);
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}
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if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType()))
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return LowerFixedLengthVectorSetccToSVE(Op, DAG);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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@ -15456,3 +15460,31 @@ SDValue AArch64TargetLowering::LowerToScalableOp(SDValue Op,
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auto ScalableRes = DAG.getNode(Op.getOpcode(), SDLoc(Op), ContainerVT, Ops);
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return convertFromScalableVector(DAG, VT, ScalableRes);
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}
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SDValue AArch64TargetLowering::LowerFixedLengthVectorSetccToSVE(
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SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT InVT = Op.getOperand(0).getValueType();
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EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT);
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assert(useSVEForFixedLengthVectorVT(InVT) &&
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"Only expected to lower fixed length vector operation!");
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assert(Op.getValueType() == InVT.changeTypeToInteger() &&
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"Expected integer result of the same bit length as the inputs!");
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// Expand floating point vector comparisons.
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if (InVT.isFloatingPoint())
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return SDValue();
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auto Op1 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(0));
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auto Op2 = convertToScalableVector(DAG, ContainerVT, Op.getOperand(1));
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auto Pg = getPredicateForFixedLengthVector(DAG, DL, InVT);
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EVT CmpVT = Pg.getValueType();
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SmallVector<SDValue, 4> CmpOps = {Pg, Op1, Op2, Op.getOperand(2)};
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auto Cmp = DAG.getNode(AArch64ISD::SETCC_MERGE_ZERO, DL, CmpVT, CmpOps);
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EVT PromoteVT = ContainerVT.changeTypeToInteger();
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auto Promote = DAG.getBoolExtOrTrunc(Cmp, DL, PromoteVT, InVT);
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return convertFromScalableVector(DAG, Op.getValueType(), Promote);
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}
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@ -907,6 +907,7 @@ private:
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SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op,
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SelectionDAG &DAG) const;
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SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op,
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SelectionDAG &DAG) const;
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631
test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
Normal file
631
test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
Normal file
@ -0,0 +1,631 @@
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; RUN: llc -aarch64-sve-vector-bits-min=128 -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE
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; RUN: llc -aarch64-sve-vector-bits-min=256 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256
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; RUN: llc -aarch64-sve-vector-bits-min=384 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK
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; RUN: llc -aarch64-sve-vector-bits-min=512 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=640 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=768 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=896 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE when its registers are no bigger than NEON.
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; NO_SVE-NOT: z{0-9}
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;
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; ICMP EQ
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;
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; Don't use SVE for 64-bit vectors.
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define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
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; CHECK-LABEL: icmp_eq_v8i8:
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; CHECK: cmeq v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%cmp = icmp eq <8 x i8> %op1, %op2
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%sext = sext <8 x i1> %cmp to <8 x i8>
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ret <8 x i8> %sext
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}
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; Don't use SVE for 128-bit vectors.
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define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
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; CHECK-LABEL: icmp_eq_v16i8:
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; CHECK: cmeq v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%cmp = icmp eq <16 x i8> %op1, %op2
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%sext = sext <16 x i1> %cmp to <16 x i8>
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ret <16 x i8> %sext
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}
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define void @icmp_eq_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v32i8:
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; CHECK: ptrue [[PG:p[0-9]+]].b, vl32
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; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
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; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
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; CHECK-NEXT: mov [[SEXT:z[0-9]+]].b, [[CMP]]/z, #-1
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; CHECK-NEXT: st1b { [[SEXT]].b }, [[PG]], [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i8>, <32 x i8>* %a
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%op2 = load <32 x i8>, <32 x i8>* %b
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%cmp = icmp eq <32 x i8> %op1, %op2
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%sext = sext <32 x i1> %cmp to <32 x i8>
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store <32 x i8> %sext, <32 x i8>* %a
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ret void
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}
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define void @icmp_eq_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v64i8:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64
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; VBITS_GE_512-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
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; VBITS_GE_512-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
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; VBITS_GE_512-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
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; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].b, [[CMP]]/z, #-1
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; VBITS_GE_512-NEXT: st1b { [[SEXT]].b }, [[PG]], [x0]
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation
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; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
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; VBITS_EQ_256-DAG: mov w[[OFF_HI:[0-9]+]], #32
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; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
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; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[OFF_HI]]]
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; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
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; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[OFF_HI]]]
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; VBITS_EQ_256-DAG: cmpeq [[CMP_LO:p[0-9]+]].b, [[PG]]/z, [[OP1_LO]].b, [[OP2_LO]].b
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; VBITS_EQ_256-DAG: cmpeq [[CMP_HI:p[0-9]+]].b, [[PG]]/z, [[OP1_HI]].b, [[OP2_HI]].b
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; VBITS_EQ_256-DAG: mov [[SEXT_LO:z[0-9]+]].b, [[CMP_LO]]/z, #-1
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; VBITS_EQ_256-DAG: mov [[SEXT_HI:z[0-9]+]].b, [[CMP_HI]]/z, #-1
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; VBITS_EQ_256-DAG: st1b { [[SEXT_LO]].b }, [[PG]], [x0]
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; VBITS_EQ_256-DAG: st1b { [[SEXT_HI]].b }, [[PG]], [x0, x[[OFF_HI]]]
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; VBITS_EQ_256-NEXT: ret
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%op1 = load <64 x i8>, <64 x i8>* %a
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%op2 = load <64 x i8>, <64 x i8>* %b
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%cmp = icmp eq <64 x i8> %op1, %op2
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%sext = sext <64 x i1> %cmp to <64 x i8>
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store <64 x i8> %sext, <64 x i8>* %a
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ret void
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}
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define void @icmp_eq_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v128i8:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128
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; VBITS_GE_1024-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
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; VBITS_GE_1024-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
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; VBITS_GE_1024-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
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; VBITS_GE_1024-NEXT: mov [[SEXT:z[0-9]+]].b, [[CMP]]/z, #-1
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; VBITS_GE_1024-NEXT: st1b { [[SEXT]].b }, [[PG]], [x0]
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; VBITS_GE_1024-NEXT: ret
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%op1 = load <128 x i8>, <128 x i8>* %a
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%op2 = load <128 x i8>, <128 x i8>* %b
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%cmp = icmp eq <128 x i8> %op1, %op2
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%sext = sext <128 x i1> %cmp to <128 x i8>
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store <128 x i8> %sext, <128 x i8>* %a
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ret void
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}
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define void @icmp_eq_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v256i8:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256
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; VBITS_GE_2048-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
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; VBITS_GE_2048-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
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; VBITS_GE_2048-NEXT: cmpeq [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
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; VBITS_GE_2048-NEXT: mov [[SEXT:z[0-9]+]].b, [[CMP]]/z, #-1
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; VBITS_GE_2048-NEXT: st1b { [[SEXT]].b }, [[PG]], [x0]
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; VBITS_GE_2048-NEXT: ret
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%op1 = load <256 x i8>, <256 x i8>* %a
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%op2 = load <256 x i8>, <256 x i8>* %b
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%cmp = icmp eq <256 x i8> %op1, %op2
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%sext = sext <256 x i1> %cmp to <256 x i8>
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store <256 x i8> %sext, <256 x i8>* %a
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
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; CHECK-LABEL: icmp_eq_v4i16:
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; CHECK: cmeq v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%cmp = icmp eq <4 x i16> %op1, %op2
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%sext = sext <4 x i1> %cmp to <4 x i16>
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ret <4 x i16> %sext
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}
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; Don't use SVE for 128-bit vectors.
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define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
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; CHECK-LABEL: icmp_eq_v8i16:
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; CHECK: cmeq v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%cmp = icmp eq <8 x i16> %op1, %op2
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%sext = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %sext
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}
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define void @icmp_eq_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v16i16:
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; CHECK: ptrue [[PG:p[0-9]+]].h, vl16
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; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
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; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
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; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
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; CHECK-NEXT: mov [[SEXT:z[0-9]+]].h, [[CMP]]/z, #-1
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; CHECK-NEXT: st1h { [[SEXT]].h }, [[PG]], [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i16>, <16 x i16>* %a
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%op2 = load <16 x i16>, <16 x i16>* %b
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%cmp = icmp eq <16 x i16> %op1, %op2
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%sext = sext <16 x i1> %cmp to <16 x i16>
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store <16 x i16> %sext, <16 x i16>* %a
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ret void
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}
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define void @icmp_eq_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v32i16:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
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; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
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; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
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; VBITS_GE_512-NEXT: cmpeq [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
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; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].h, [[CMP]]/z, #-1
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; VBITS_GE_512-NEXT: st1h { [[SEXT]].h }, [[PG]], [x0]
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; VBITS_GE_512-NEXT: ret
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; Ensure sensible type legalisation
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; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
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; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
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; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32
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; VBITS_EQ_256-DAG: ld1h { [[OP1_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
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; VBITS_EQ_256-DAG: ld1h { [[OP1_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
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; VBITS_EQ_256-DAG: ld1h { [[OP2_LO:z[0-9]+]].h }, [[PG]]/z, [x1]
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; VBITS_EQ_256-DAG: ld1h { [[OP2_HI:z[0-9]+]].h }, [[PG]]/z, [x[[B_HI]]]
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; VBITS_EQ_256-DAG: cmpeq [[CMP_LO:p[0-9]+]].h, [[PG]]/z, [[OP1_LO]].h, [[OP2_LO]].h
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; VBITS_EQ_256-DAG: cmpeq [[CMP_HI:p[0-9]+]].h, [[PG]]/z, [[OP1_HI]].h, [[OP2_HI]].h
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; VBITS_EQ_256-DAG: mov [[SEXT_LO:z[0-9]+]].h, [[CMP_LO]]/z, #-1
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; VBITS_EQ_256-DAG: mov [[SEXT_HI:z[0-9]+]].h, [[CMP_HI]]/z, #-1
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; VBITS_EQ_256-DAG: st1h { [[SEXT_LO]].h }, [[PG]], [x0]
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; VBITS_EQ_256-DAG: st1h { [[SEXT_HI]].h }, [[PG]], [x[[A_HI]]]
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; VBITS_EQ_256-NEXT: ret
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%op1 = load <32 x i16>, <32 x i16>* %a
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%op2 = load <32 x i16>, <32 x i16>* %b
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%cmp = icmp eq <32 x i16> %op1, %op2
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%sext = sext <32 x i1> %cmp to <32 x i16>
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store <32 x i16> %sext, <32 x i16>* %a
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ret void
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}
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define void @icmp_eq_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
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; CHECK-LABEL: icmp_eq_v64i16:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64
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||||
; VBITS_GE_1024-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_1024-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_1024-NEXT: cmpeq [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
|
||||
; VBITS_GE_1024-NEXT: mov [[SEXT:z[0-9]+]].h, [[CMP]]/z, #-1
|
||||
; VBITS_GE_1024-NEXT: st1h { [[SEXT]].h }, [[PG]], [x0]
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op1 = load <64 x i16>, <64 x i16>* %a
|
||||
%op2 = load <64 x i16>, <64 x i16>* %b
|
||||
%cmp = icmp eq <64 x i16> %op1, %op2
|
||||
%sext = sext <64 x i1> %cmp to <64 x i16>
|
||||
store <64 x i16> %sext, <64 x i16>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v128i16:
|
||||
; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128
|
||||
; VBITS_GE_2048-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_2048-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_2048-NEXT: cmpeq [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
|
||||
; VBITS_GE_2048-NEXT: mov [[SEXT:z[0-9]+]].h, [[CMP]]/z, #-1
|
||||
; VBITS_GE_2048-NEXT: st1h { [[SEXT]].h }, [[PG]], [x0]
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op1 = load <128 x i16>, <128 x i16>* %a
|
||||
%op2 = load <128 x i16>, <128 x i16>* %b
|
||||
%cmp = icmp eq <128 x i16> %op1, %op2
|
||||
%sext = sext <128 x i1> %cmp to <128 x i16>
|
||||
store <128 x i16> %sext, <128 x i16>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
; Don't use SVE for 64-bit vectors.
|
||||
define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v2i32:
|
||||
; CHECK: cmeq v0.2s, v0.2s, v1.2s
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = icmp eq <2 x i32> %op1, %op2
|
||||
%sext = sext <2 x i1> %cmp to <2 x i32>
|
||||
ret <2 x i32> %sext
|
||||
}
|
||||
|
||||
; Don't use SVE for 128-bit vectors.
|
||||
define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v4i32:
|
||||
; CHECK: cmeq v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = icmp eq <4 x i32> %op1, %op2
|
||||
%sext = sext <4 x i1> %cmp to <4 x i32>
|
||||
ret <4 x i32> %sext
|
||||
}
|
||||
|
||||
define void @icmp_eq_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v8i32:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
|
||||
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].s, [[PG]]/z, [[OP1]].s, [[OP2]].s
|
||||
; CHECK-NEXT: mov [[SEXT:z[0-9]+]].s, [[CMP]]/z, #-1
|
||||
; CHECK-NEXT: st1w { [[SEXT]].s }, [[PG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x i32>, <8 x i32>* %a
|
||||
%op2 = load <8 x i32>, <8 x i32>* %b
|
||||
%cmp = icmp eq <8 x i32> %op1, %op2
|
||||
%sext = sext <8 x i1> %cmp to <8 x i32>
|
||||
store <8 x i32> %sext, <8 x i32>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v16i32:
|
||||
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
|
||||
; VBITS_GE_512-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_512-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_512-NEXT: cmpeq [[CMP:p[0-9]+]].s, [[PG]]/z, [[OP1]].s, [[OP2]].s
|
||||
; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].s, [[CMP]]/z, #-1
|
||||
; VBITS_GE_512-NEXT: st1w { [[SEXT]].s }, [[PG]], [x0]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
|
||||
; Ensure sensible type legalisation
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
|
||||
; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
|
||||
; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32
|
||||
; VBITS_EQ_256-DAG: ld1w { [[OP1_LO:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_EQ_256-DAG: ld1w { [[OP1_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]]
|
||||
; VBITS_EQ_256-DAG: ld1w { [[OP2_LO:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; VBITS_EQ_256-DAG: ld1w { [[OP2_HI:z[0-9]+]].s }, [[PG]]/z, [x[[B_HI]]]
|
||||
; VBITS_EQ_256-DAG: cmpeq [[CMP_LO:p[0-9]+]].s, [[PG]]/z, [[OP1_LO]].s, [[OP2_LO]].s
|
||||
; VBITS_EQ_256-DAG: cmpeq [[CMP_HI:p[0-9]+]].s, [[PG]]/z, [[OP1_HI]].s, [[OP2_HI]].s
|
||||
; VBITS_EQ_256-DAG: mov [[SEXT_LO:z[0-9]+]].s, [[CMP_LO]]/z, #-1
|
||||
; VBITS_EQ_256-DAG: mov [[SEXT_HI:z[0-9]+]].s, [[CMP_HI]]/z, #-1
|
||||
; VBITS_EQ_256-DAG: st1w { [[SEXT_LO]].s }, [[PG]], [x0]
|
||||
; VBITS_EQ_256-DAG: st1w { [[SEXT_HI]].s }, [[PG]], [x[[A_HI]]]
|
||||
; VBITS_EQ_256-NEXT: ret
|
||||
%op1 = load <16 x i32>, <16 x i32>* %a
|
||||
%op2 = load <16 x i32>, <16 x i32>* %b
|
||||
%cmp = icmp eq <16 x i32> %op1, %op2
|
||||
%sext = sext <16 x i1> %cmp to <16 x i32>
|
||||
store <16 x i32> %sext, <16 x i32>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v32i32:
|
||||
; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
|
||||
; VBITS_GE_1024-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_1024-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_1024-NEXT: cmpeq [[CMP:p[0-9]+]].s, [[PG]]/z, [[OP1]].s, [[OP2]].s
|
||||
; VBITS_GE_1024-NEXT: mov [[SEXT:z[0-9]+]].s, [[CMP]]/z, #-1
|
||||
; VBITS_GE_1024-NEXT: st1w { [[SEXT]].s }, [[PG]], [x0]
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op1 = load <32 x i32>, <32 x i32>* %a
|
||||
%op2 = load <32 x i32>, <32 x i32>* %b
|
||||
%cmp = icmp eq <32 x i32> %op1, %op2
|
||||
%sext = sext <32 x i1> %cmp to <32 x i32>
|
||||
store <32 x i32> %sext, <32 x i32>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v64i32:
|
||||
; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
|
||||
; VBITS_GE_2048-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_2048-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_2048-NEXT: cmpeq [[CMP:p[0-9]+]].s, [[PG]]/z, [[OP1]].s, [[OP2]].s
|
||||
; VBITS_GE_2048-NEXT: mov [[SEXT:z[0-9]+]].s, [[CMP]]/z, #-1
|
||||
; VBITS_GE_2048-NEXT: st1w { [[SEXT]].s }, [[PG]], [x0]
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op1 = load <64 x i32>, <64 x i32>* %a
|
||||
%op2 = load <64 x i32>, <64 x i32>* %b
|
||||
%cmp = icmp eq <64 x i32> %op1, %op2
|
||||
%sext = sext <64 x i1> %cmp to <64 x i32>
|
||||
store <64 x i32> %sext, <64 x i32>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
; Don't use SVE for 64-bit vectors.
|
||||
define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v1i64:
|
||||
; CHECK: cmeq d0, d0, d1
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = icmp eq <1 x i64> %op1, %op2
|
||||
%sext = sext <1 x i1> %cmp to <1 x i64>
|
||||
ret <1 x i64> %sext
|
||||
}
|
||||
|
||||
; Don't use SVE for 128-bit vectors.
|
||||
define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v2i64:
|
||||
; CHECK: cmeq v0.2d, v0.2d, v1.2d
|
||||
; CHECK-NEXT: ret
|
||||
%cmp = icmp eq <2 x i64> %op1, %op2
|
||||
%sext = sext <2 x i1> %cmp to <2 x i64>
|
||||
ret <2 x i64> %sext
|
||||
}
|
||||
|
||||
define void @icmp_eq_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v4i64:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
|
||||
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; CHECK-NEXT: cmpeq [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP1]].d, [[OP2]].d
|
||||
; CHECK-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; CHECK-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x i64>, <4 x i64>* %a
|
||||
%op2 = load <4 x i64>, <4 x i64>* %b
|
||||
%cmp = icmp eq <4 x i64> %op1, %op2
|
||||
%sext = sext <4 x i1> %cmp to <4 x i64>
|
||||
store <4 x i64> %sext, <4 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v8i64:
|
||||
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
|
||||
; VBITS_GE_512-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_512-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_512-NEXT: cmpeq [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP1]].d, [[OP2]].d
|
||||
; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; VBITS_GE_512-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
|
||||
; Ensure sensible type legalisation
|
||||
; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
|
||||
; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
|
||||
; VBITS_EQ_256-DAG: add x[[B_HI:[0-9]+]], x1, #32
|
||||
; VBITS_EQ_256-DAG: ld1d { [[OP1_LO:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_EQ_256-DAG: ld1d { [[OP1_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]]
|
||||
; VBITS_EQ_256-DAG: ld1d { [[OP2_LO:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_EQ_256-DAG: ld1d { [[OP2_HI:z[0-9]+]].d }, [[PG]]/z, [x[[B_HI]]]
|
||||
; VBITS_EQ_256-DAG: cmpeq [[CMP_LO:p[0-9]+]].d, [[PG]]/z, [[OP1_LO]].d, [[OP2_LO]].d
|
||||
; VBITS_EQ_256-DAG: cmpeq [[CMP_HI:p[0-9]+]].d, [[PG]]/z, [[OP1_HI]].d, [[OP2_HI]].d
|
||||
; VBITS_EQ_256-DAG: mov [[SEXT_LO:z[0-9]+]].d, [[CMP_LO]]/z, #-1
|
||||
; VBITS_EQ_256-DAG: mov [[SEXT_HI:z[0-9]+]].d, [[CMP_HI]]/z, #-1
|
||||
; VBITS_EQ_256-DAG: st1d { [[SEXT_LO]].d }, [[PG]], [x0]
|
||||
; VBITS_EQ_256-DAG: st1d { [[SEXT_HI]].d }, [[PG]], [x[[A_HI]]]
|
||||
; VBITS_EQ_256-NEXT: ret
|
||||
%op1 = load <8 x i64>, <8 x i64>* %a
|
||||
%op2 = load <8 x i64>, <8 x i64>* %b
|
||||
%cmp = icmp eq <8 x i64> %op1, %op2
|
||||
%sext = sext <8 x i1> %cmp to <8 x i64>
|
||||
store <8 x i64> %sext, <8 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v16i64:
|
||||
; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
|
||||
; VBITS_GE_1024-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_1024-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_1024-NEXT: cmpeq [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP1]].d, [[OP2]].d
|
||||
; VBITS_GE_1024-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; VBITS_GE_1024-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op1 = load <16 x i64>, <16 x i64>* %a
|
||||
%op2 = load <16 x i64>, <16 x i64>* %b
|
||||
%cmp = icmp eq <16 x i64> %op1, %op2
|
||||
%sext = sext <16 x i1> %cmp to <16 x i64>
|
||||
store <16 x i64> %sext, <16 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @icmp_eq_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_eq_v32i64:
|
||||
; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
|
||||
; VBITS_GE_2048-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_2048-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_2048-NEXT: cmpeq [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP1]].d, [[OP2]].d
|
||||
; VBITS_GE_2048-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; VBITS_GE_2048-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op1 = load <32 x i64>, <32 x i64>* %a
|
||||
%op2 = load <32 x i64>, <32 x i64>* %b
|
||||
%cmp = icmp eq <32 x i64> %op1, %op2
|
||||
%sext = sext <32 x i1> %cmp to <32 x i64>
|
||||
store <32 x i64> %sext, <32 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP NE
|
||||
;
|
||||
|
||||
define void @icmp_ne_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_ne_v32i8:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].b, vl32
|
||||
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
|
||||
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
|
||||
; CHECK-NEXT: cmpne [[CMP:p[0-9]+]].b, [[PG]]/z, [[OP1]].b, [[OP2]].b
|
||||
; CHECK-NEXT: mov [[SEXT:z[0-9]+]].b, [[CMP]]/z, #-1
|
||||
; CHECK-NEXT: st1b { [[SEXT]].b }, [[PG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <32 x i8>, <32 x i8>* %a
|
||||
%op2 = load <32 x i8>, <32 x i8>* %b
|
||||
%cmp = icmp ne <32 x i8> %op1, %op2
|
||||
%sext = sext <32 x i1> %cmp to <32 x i8>
|
||||
store <32 x i8> %sext, <32 x i8>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP SGE
|
||||
;
|
||||
|
||||
define void @icmp_sge_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_sge_v32i16:
|
||||
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
|
||||
; VBITS_GE_512-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_512-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_512-NEXT: cmpge [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
|
||||
; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].h, [[CMP]]/z, #-1
|
||||
; VBITS_GE_512-NEXT: st1h { [[SEXT]].h }, [[PG]], [x0]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op1 = load <32 x i16>, <32 x i16>* %a
|
||||
%op2 = load <32 x i16>, <32 x i16>* %b
|
||||
%cmp = icmp sge <32 x i16> %op1, %op2
|
||||
%sext = sext <32 x i1> %cmp to <32 x i16>
|
||||
store <32 x i16> %sext, <32 x i16>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP SGT
|
||||
;
|
||||
|
||||
define void @icmp_sgt_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_sgt_v16i16:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].h, vl16
|
||||
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
|
||||
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
|
||||
; CHECK-NEXT: cmpgt [[CMP:p[0-9]+]].h, [[PG]]/z, [[OP1]].h, [[OP2]].h
|
||||
; CHECK-NEXT: mov [[SEXT:z[0-9]+]].h, [[CMP]]/z, #-1
|
||||
; CHECK-NEXT: st1h { [[SEXT]].h }, [[PG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <16 x i16>, <16 x i16>* %a
|
||||
%op2 = load <16 x i16>, <16 x i16>* %b
|
||||
%cmp = icmp sgt <16 x i16> %op1, %op2
|
||||
%sext = sext <16 x i1> %cmp to <16 x i16>
|
||||
store <16 x i16> %sext, <16 x i16>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP SLE
|
||||
;
|
||||
|
||||
define void @icmp_sle_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_sle_v16i32:
|
||||
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
|
||||
; VBITS_GE_512-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_512-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_512-NEXT: cmpge [[CMP:p[0-9]+]].s, [[PG]]/z, [[OP2]].s, [[OP1]].s
|
||||
; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].s, [[CMP]]/z, #-1
|
||||
; VBITS_GE_512-NEXT: st1w { [[SEXT]].s }, [[PG]], [x0]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op1 = load <16 x i32>, <16 x i32>* %a
|
||||
%op2 = load <16 x i32>, <16 x i32>* %b
|
||||
%cmp = icmp sle <16 x i32> %op1, %op2
|
||||
%sext = sext <16 x i1> %cmp to <16 x i32>
|
||||
store <16 x i32> %sext, <16 x i32>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP SLT
|
||||
;
|
||||
|
||||
define void @icmp_slt_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_slt_v8i32:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
|
||||
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
|
||||
; CHECK-NEXT: cmpgt [[CMP:p[0-9]+]].s, [[PG]]/z, [[OP2]].s, [[OP1]].s
|
||||
; CHECK-NEXT: mov [[SEXT:z[0-9]+]].s, [[CMP]]/z, #-1
|
||||
; CHECK-NEXT: st1w { [[SEXT]].s }, [[PG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <8 x i32>, <8 x i32>* %a
|
||||
%op2 = load <8 x i32>, <8 x i32>* %b
|
||||
%cmp = icmp slt <8 x i32> %op1, %op2
|
||||
%sext = sext <8 x i1> %cmp to <8 x i32>
|
||||
store <8 x i32> %sext, <8 x i32>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP UGE
|
||||
;
|
||||
|
||||
define void @icmp_uge_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_uge_v8i64:
|
||||
; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
|
||||
; VBITS_GE_512-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_512-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_512-NEXT: cmphs [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP1]].d, [[OP2]].d
|
||||
; VBITS_GE_512-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; VBITS_GE_512-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; VBITS_GE_512-NEXT: ret
|
||||
%op1 = load <8 x i64>, <8 x i64>* %a
|
||||
%op2 = load <8 x i64>, <8 x i64>* %b
|
||||
%cmp = icmp uge <8 x i64> %op1, %op2
|
||||
%sext = sext <8 x i1> %cmp to <8 x i64>
|
||||
store <8 x i64> %sext, <8 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP UGT
|
||||
;
|
||||
|
||||
define void @icmp_ugt_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_ugt_v4i64:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
|
||||
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; CHECK-NEXT: cmphi [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP1]].d, [[OP2]].d
|
||||
; CHECK-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; CHECK-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; CHECK-NEXT: ret
|
||||
%op1 = load <4 x i64>, <4 x i64>* %a
|
||||
%op2 = load <4 x i64>, <4 x i64>* %b
|
||||
%cmp = icmp ugt <4 x i64> %op1, %op2
|
||||
%sext = sext <4 x i1> %cmp to <4 x i64>
|
||||
store <4 x i64> %sext, <4 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP ULE
|
||||
;
|
||||
|
||||
define void @icmp_ule_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_ule_v16i64:
|
||||
; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
|
||||
; VBITS_GE_1024-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_1024-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_1024-NEXT: cmphs [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP2]].d, [[OP1]].d
|
||||
; VBITS_GE_1024-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; VBITS_GE_1024-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; VBITS_GE_1024-NEXT: ret
|
||||
%op1 = load <16 x i64>, <16 x i64>* %a
|
||||
%op2 = load <16 x i64>, <16 x i64>* %b
|
||||
%cmp = icmp ule <16 x i64> %op1, %op2
|
||||
%sext = sext <16 x i1> %cmp to <16 x i64>
|
||||
store <16 x i64> %sext, <16 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ICMP ULT
|
||||
;
|
||||
|
||||
define void @icmp_ult_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
|
||||
; CHECK-LABEL: icmp_ult_v32i64:
|
||||
; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
|
||||
; VBITS_GE_2048-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
|
||||
; VBITS_GE_2048-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
|
||||
; VBITS_GE_2048-NEXT: cmphi [[CMP:p[0-9]+]].d, [[PG]]/z, [[OP2]].d, [[OP1]].d
|
||||
; VBITS_GE_2048-NEXT: mov [[SEXT:z[0-9]+]].d, [[CMP]]/z, #-1
|
||||
; VBITS_GE_2048-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
|
||||
; VBITS_GE_2048-NEXT: ret
|
||||
%op1 = load <32 x i64>, <32 x i64>* %a
|
||||
%op2 = load <32 x i64>, <32 x i64>* %b
|
||||
%cmp = icmp ult <32 x i64> %op1, %op2
|
||||
%sext = sext <32 x i1> %cmp to <32 x i64>
|
||||
store <32 x i64> %sext, <32 x i64>* %a
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve" }
|
||||
@ -92,8 +92,8 @@ bb1:
|
||||
define <8 x i1> @no_warn_dropped_scalable(<8 x i32>* %in) #0 {
|
||||
; CHECK-LABEL: no_warn_dropped_scalable:
|
||||
; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
|
||||
; CHECK: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x0]
|
||||
; CHECK-COUNT-8: cmp w{{[0-9]+}}, #0
|
||||
; CHECK: ld1w { [[A:z[0-9]+]].s }, [[PG]]/z, [x0]
|
||||
; CHECK: cmpgt p{{[0-9]}}.s, [[PG]]/z, [[A]].s, z{{[0-9]+}}.s
|
||||
; CHECK: ret
|
||||
%a = load <8 x i32>, <8 x i32>* %in
|
||||
br label %bb1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user