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[ARM][MVE] VPT Blocks: findVCMPToFoldIntoVPS
This is a recommit of D71330, but with a few things fixed and changed: 1) ReachingDefAnalysis: this was not running with optnone as it was checking skipFunction(), which other analysis passes don't do. I guess this is a copy-paste from a codegen pass. 2) VPTBlockPass: here I've added skipFunction(), because like most/all optimisations, we don't want to run this with optnone. This fixes the issues with the initial/previous commit: the VPTBlockPass was running with optnone, but ReachingDefAnalysis wasn't, and so VPTBlockPass was crashing querying ReachingDefAnalysis. I've added test case mve-vpt-block-optnone.mir to check that we don't run VPTBlock with optnone. Differential Revision: https://reviews.llvm.org/D71470
This commit is contained in:
Sjoerd Meijer
parent
71c2db1510
commit
038287e275
@ -133,8 +133,6 @@ void ReachingDefAnalysis::processBasicBlock(
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}
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bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
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if (skipFunction(mf.getFunction()))
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return false;
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MF = &mf;
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TRI = MF->getSubtarget().getRegisterInfo();
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@ -22,9 +22,9 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/ReachingDefAnalysis.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include <cassert>
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#include <new>
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@ -37,16 +37,21 @@ namespace {
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class MVEVPTBlock : public MachineFunctionPass {
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public:
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static char ID;
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const Thumb2InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MVEVPTBlock() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<ReachingDefAnalysis>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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MachineFunctionProperties::Property::NoVRegs).set(
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MachineFunctionProperties::Property::TracksLiveness);
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}
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StringRef getPassName() const override {
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@ -55,6 +60,9 @@ namespace {
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private:
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bool InsertVPTBlocks(MachineBasicBlock &MBB);
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const Thumb2InstrInfo *TII = nullptr;
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ReachingDefAnalysis *RDA = nullptr;
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};
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char MVEVPTBlock::ID = 0;
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@ -63,41 +71,32 @@ namespace {
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INITIALIZE_PASS(MVEVPTBlock, DEBUG_TYPE, "ARM MVE VPT block pass", false, false)
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static MachineInstr *findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI,
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const TargetRegisterInfo *TRI,
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static MachineInstr *findVCMPToFoldIntoVPST(MachineInstr *MI,
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ReachingDefAnalysis *RDA,
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unsigned &NewOpcode) {
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// Search backwards to the instruction that defines VPR. This may or not
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// be a VCMP, we check that after this loop. If we find another instruction
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// that reads cpsr, we return nullptr.
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MachineBasicBlock::iterator CmpMI = MI;
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while (CmpMI != MI->getParent()->begin()) {
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--CmpMI;
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if (CmpMI->modifiesRegister(ARM::VPR, TRI))
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break;
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if (CmpMI->readsRegister(ARM::VPR, TRI))
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break;
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}
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if (CmpMI == MI)
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return nullptr;
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NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode());
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if (NewOpcode == 0)
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// First, search backwards to the instruction that defines VPR
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auto *Def = RDA->getReachingMIDef(MI, ARM::VPR);
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if (!Def)
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return nullptr;
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// Search forward from CmpMI to MI, checking if either register was def'd
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if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI),
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MI, TRI))
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// Now check that Def is a VCMP
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if (!(NewOpcode = VCMPOpcodeToVPT(Def->getOpcode())))
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return nullptr;
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if (registerDefinedBetween(CmpMI->getOperand(2).getReg(), std::next(CmpMI),
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MI, TRI))
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// Check that Def's operands are not defined between the VCMP and MI, i.e.
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// check that they have the same reaching def.
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if (!RDA->hasSameReachingDef(Def, MI, Def->getOperand(1).getReg()) ||
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!RDA->hasSameReachingDef(Def, MI, Def->getOperand(2).getReg()))
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return nullptr;
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return &*CmpMI;
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return Def;
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}
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bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
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bool Modified = false;
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MachineBasicBlock::instr_iterator MBIter = Block.instr_begin();
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MachineBasicBlock::instr_iterator EndIter = Block.instr_end();
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SmallVector<MachineInstr *, 4> RemovedVCMPs;
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while (MBIter != EndIter) {
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MachineInstr *MI = &*MBIter;
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@ -143,7 +142,7 @@ bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
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// a VPST directly
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MachineInstrBuilder MIBuilder;
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unsigned NewOpcode;
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MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode);
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MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, RDA, NewOpcode);
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if (VCMP) {
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LLVM_DEBUG(dbgs() << " folding VCMP into VPST: "; VCMP->dump());
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MIBuilder = BuildMI(Block, MI, dl, TII->get(NewOpcode));
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@ -151,7 +150,11 @@ bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
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MIBuilder.add(VCMP->getOperand(1));
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MIBuilder.add(VCMP->getOperand(2));
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MIBuilder.add(VCMP->getOperand(3));
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VCMP->eraseFromParent();
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// We delay removing the actual VCMP instruction by saving it to a list
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// and deleting all instructions in this list in one go after we have
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// created the VPT blocks. We do this in order not to invalidate the
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// ReachingDefAnalysis that is queried by 'findVCMPToFoldIntoVPST'.
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RemovedVCMPs.push_back(VCMP);
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} else {
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MIBuilder = BuildMI(Block, MI, dl, TII->get(ARM::MVE_VPST));
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MIBuilder.addImm(BlockMask);
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@ -162,10 +165,17 @@ bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
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Modified = true;
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}
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for (auto *I : RemovedVCMPs)
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I->eraseFromParent();
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return Modified;
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}
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bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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const ARMSubtarget &STI =
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static_cast<const ARMSubtarget &>(Fn.getSubtarget());
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@ -173,7 +183,7 @@ bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
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return false;
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TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
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TRI = STI.getRegisterInfo();
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RDA = &getAnalysis<ReachingDefAnalysis>();
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LLVM_DEBUG(dbgs() << "********** ARM MVE VPT BLOCKS **********\n"
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<< "********** Function: " << Fn.getName() << '\n');
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@ -144,6 +144,7 @@
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: If Converter
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: MVE VPT block insertion pass
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; CHECK-NEXT: Thumb IT blocks insertion pass
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; CHECK-NEXT: MachineDominator Tree Construction
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128
test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
Normal file
128
test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir
Normal file
@ -0,0 +1,128 @@
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# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-unknown-eabihf"
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define dso_local <4 x i32> @foo(<4 x i32>* %src, <4 x i32>* %src2, <4 x i32>* %src3, <4 x i32>* %dest, <4 x i32>* %dest2, <4 x i32>* %dest3, <4 x float> %a1) local_unnamed_addr #0 {
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entry:
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%c = fcmp one <4 x float> %a1, zeroinitializer
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%w = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %src, i32 4, <4 x i1> %c, <4 x i32> undef)
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tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %w, <4 x i32>* %dest, i32 4, <4 x i1> %c)
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%w2 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %src2, i32 4, <4 x i1> %c, <4 x i32> undef)
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tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %w2, <4 x i32>* %dest2, i32 4, <4 x i1> %c)
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%w3 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %src3, i32 4, <4 x i1> %c, <4 x i32> undef)
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tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %w3, <4 x i32>* %dest3, i32 4, <4 x i1> %c)
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ret <4 x i32> %w3
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}
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #3
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attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+fp-armv8d16sp,+fp16,+fpregs,+fullfp16,+hwdiv,+lob,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { argmemonly nounwind readonly willreturn }
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attributes #3 = { argmemonly nounwind willreturn }
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attributes #4 = { noduplicate nounwind }
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attributes #5 = { nounwind }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"min_enum_size", i32 4}
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!2 = !{!"clang version 10.0.0 (http://github.com/llvm/llvm-project 90450197deaf91160a22825e6746d998aad05704)"}
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...
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---
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name: foo
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$q0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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- { id: 0, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $q0, $r0, $r1, $r2, $lr
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; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr {
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; CHECK: MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr
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; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr :: (load 16 from %ir.src, align 4)
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; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $r3, 0, 1, internal renamable $vpr :: (store 16 into %ir.dest, align 4)
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; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, internal renamable $vpr :: (load 16 from %ir.src2, align 4)
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; CHECK: MVE_VSTRWU32 internal killed renamable $q0, killed renamable $lr, 0, 1, internal renamable $vpr :: (store 16 into %ir.dest2, align 4)
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; CHECK: }
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; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $r2, implicit killed $r12 {
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load 16 from %ir.src3, align 4)
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; CHECK: MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store 16 into %ir.dest3, align 4)
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; CHECK: }
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$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r7 = frame-setup tMOVr killed $sp, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_register $r7
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renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load 4 from %fixed-stack.1)
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renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load 4 from %fixed-stack.2)
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renamable $r3 = t2LDRi12 $r7, 8, 14, $noreg :: (load 4 from %fixed-stack.3)
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renamable $vpr = MVE_VCMPf32r renamable $q0, $zr, 10, 0, $noreg
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renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, renamable $vpr :: (load 16 from %ir.src, align 4)
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MVE_VSTRWU32 killed renamable $q0, killed renamable $r3, 0, 1, renamable $vpr :: (store 16 into %ir.dest, align 4)
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renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 1, renamable $vpr :: (load 16 from %ir.src2, align 4)
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MVE_VSTRWU32 killed renamable $q0, killed renamable $lr, 0, 1, renamable $vpr :: (store 16 into %ir.dest2, align 4)
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renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load 16 from %ir.src3, align 4)
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MVE_VSTRWU32 renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store 16 into %ir.dest3, align 4)
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$sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $q0
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...
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75
test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
Normal file
75
test/CodeGen/Thumb2/mve-vpt-block-optnone.mir
Normal file
@ -0,0 +1,75 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-none-eabi"
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define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
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entry:
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%conv.i = zext i16 %p to i32
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%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
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ret <4 x float> %0
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}
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declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
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|
||||
attributes #0 = { noinline optnone nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
attributes #2 = { nounwind }
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: test_vminnmq_m_f32_v2
|
||||
alignment: 4
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$q0', virtual-reg: '' }
|
||||
- { reg: '$q1', virtual-reg: '' }
|
||||
- { reg: '$q2', virtual-reg: '' }
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 0
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 0
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
cvBytesOfCalleeSavedRegisters: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack: []
|
||||
stack: []
|
||||
constants: []
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $q0, $q1, $q2, $r0
|
||||
|
||||
; CHECK-LABEL: name: test_vminnmq_m_f32_v2
|
||||
; CHECK: liveins: $q0, $q1, $q2, $r0
|
||||
; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg
|
||||
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
|
||||
; CHECK: tBX_RET 14, $noreg, implicit $q0
|
||||
|
||||
$vpr = VMSR_P0 killed $r0, 14, $noreg
|
||||
renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
|
||||
tBX_RET 14, $noreg, implicit $q0
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user