[PowerPC] modernize test via update_llc_test_checks.py. NFC

test/CodeGen/PowerPC/expand-foldable-isel.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 ; This file mainly tests the case that the two input registers of the ISEL instruction are the same register.
@@ -22,21 +23,95 @@ target triple = "powerpc64le-unknown-linux-gnu"
 
 define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block) {
 ; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
-; Note: the following line fold the original isel (isel r4, r3, r3)
+; CHECK-GEN-ISEL-TRUE:       # %bb.0: # %entry
-; CHECK-GEN-ISEL-TRUE:    mr r4, r3
+; CHECK-GEN-ISEL-TRUE-NEXT:    mflr r0
-; CHECK-GEN-ISEL-TRUE:    isel r29, r5, r6, 4*cr5+lt
+; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-GEN-ISEL-TRUE:    blr
+; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset lr, 16
+; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset r29, -24
+; CHECK-GEN-ISEL-TRUE-NEXT:    .cfi_offset r30, -16
+; CHECK-GEN-ISEL-TRUE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-GEN-ISEL-TRUE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-GEN-ISEL-TRUE-NEXT:    std r0, 16(r1)
+; CHECK-GEN-ISEL-TRUE-NEXT:    stdu r1, -64(r1)
+; CHECK-GEN-ISEL-TRUE-NEXT:    mr r30, r3
+; CHECK-GEN-ISEL-TRUE-NEXT:    # implicit-def: $x4
+; CHECK-GEN-ISEL-TRUE-NEXT:    # implicit-def: $r29
+; CHECK-GEN-ISEL-TRUE-NEXT:    .p2align 4
+; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_1: # %while.cond11
+; CHECK-GEN-ISEL-TRUE-NEXT:    #
+; CHECK-GEN-ISEL-TRUE-NEXT:    lwz r3, 0(r3)
+; CHECK-GEN-ISEL-TRUE-NEXT:    cmplwi r3, 0
+; CHECK-GEN-ISEL-TRUE-NEXT:    beq cr0, .LBB0_3
+; CHECK-GEN-ISEL-TRUE-NEXT:  # %bb.2: # %while.body21
+; CHECK-GEN-ISEL-TRUE-NEXT:    #
+; CHECK-GEN-ISEL-TRUE-NEXT:    bl ZN3pov10pov_callocEmmPKciS1_pov
+; CHECK-GEN-ISEL-TRUE-NEXT:    nop
+; CHECK-GEN-ISEL-TRUE-NEXT:    addi r4, r29, 1
+; CHECK-GEN-ISEL-TRUE-NEXT:    srwi r6, r29, 1
+; CHECK-GEN-ISEL-TRUE-NEXT:    srawi r4, r4, 1
+; CHECK-GEN-ISEL-TRUE-NEXT:    std r3, 0(r3)
+; CHECK-GEN-ISEL-TRUE-NEXT:    addze r5, r4
+; CHECK-GEN-ISEL-TRUE-NEXT:    mr r4, r3
+; CHECK-GEN-ISEL-TRUE-NEXT:    isel r29, r5, r6, 4*cr5+lt
+; CHECK-GEN-ISEL-TRUE-NEXT:    b .LBB0_1
+; CHECK-GEN-ISEL-TRUE-NEXT:  .LBB0_3: # %lor.rhs
+; CHECK-GEN-ISEL-TRUE-NEXT:    std r30, 16(r4)
+; CHECK-GEN-ISEL-TRUE-NEXT:    addi r1, r1, 64
+; CHECK-GEN-ISEL-TRUE-NEXT:    ld r0, 16(r1)
+; CHECK-GEN-ISEL-TRUE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-GEN-ISEL-TRUE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-GEN-ISEL-TRUE-NEXT:    mtlr r0
+; CHECK-GEN-ISEL-TRUE-NEXT:    blr
 ;
 ; CHECK-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
-; CHECK:    mr r4, r3
+; CHECK:       # %bb.0: # %entry
-; CHECK:    bc 12, 4*cr5+lt, [[CASE1:.LBB[0-9_]+]]
+; CHECK-NEXT:    mflr r0
-; CHECK:   # %bb.
+; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK:    ori r29, r6, 0
+; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK:    b [[MERGE:.LBB[0-9_]+]]
+; CHECK-NEXT:    .cfi_offset r29, -24
-; CHECK:  [[CASE1]]:
+; CHECK-NEXT:    .cfi_offset r30, -16
-; CHECK:    addi r29, r5, 0
+; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
-; CHECK:  [[MERGE]]:
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK:    blr
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    mr r30, r3
+; CHECK-NEXT:    # implicit-def: $x4
+; CHECK-NEXT:    # implicit-def: $r29
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_1: # %while.cond11
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    cmplwi r3, 0
+; CHECK-NEXT:    beq cr0, .LBB0_6
+; CHECK-NEXT:  # %bb.2: # %while.body21
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bl ZN3pov10pov_callocEmmPKciS1_pov
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addi r4, r29, 1
+; CHECK-NEXT:    srwi r6, r29, 1
+; CHECK-NEXT:    srawi r4, r4, 1
+; CHECK-NEXT:    std r3, 0(r3)
+; CHECK-NEXT:    addze r5, r4
+; CHECK-NEXT:    mr r4, r3
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_4
+; CHECK-NEXT:  # %bb.3: # %while.body21
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ori r29, r6, 0
+; CHECK-NEXT:    b .LBB0_5
+; CHECK-NEXT:  .LBB0_4: # %while.body21
+; CHECK-NEXT:    #
+; CHECK-NEXT:    addi r29, r5, 0
+; CHECK-NEXT:  .LBB0_5: # %while.body21
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_1
+; CHECK-NEXT:  .LBB0_6: # %lor.rhs
+; CHECK-NEXT:    std r30, 16(r4)
+; CHECK-NEXT:    addi r1, r1, 64
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
 entry:
   br label %while.cond11