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Unaligned loads should use the VMOVUPS opcode.

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llvm-svn: 177130
This commit is contained in:
Nadav Rotem 2013-03-14 23:49:44 +00:00
parent 45229b3f0a
commit 03b60b8657
3 changed files with 13 additions and 2 deletions
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2
lib/Target/X86/X86InstrSSE.td
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@ -1009,7 +1009,7 @@ let Predicates = [HasAVX] in {
(VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
def : Pat<(store (v8i16 (extract_subvector
(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
(VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
(VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
def : Pat<(store (v16i8 (extract_subvector
(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
(VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;

2
test/CodeGen/X86/avx-load-store.ll
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@ -55,7 +55,7 @@ define void @storev16i16(<16 x i16> %a) nounwind {
; CHECK: storev16i16_01
; CHECK: vextractf128
; CHECK: vmovaps %xmm
; CHECK: vmovups %xmm
define void @storev16i16_01(<16 x i16> %a) nounwind {
store <16 x i16> %a, <16 x i16>* undef, align 4
unreachable

11
test/CodeGen/X86/vec_align_i256.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc < %s -mcpu=corei7-avx | FileCheck %s
; Make sure that we are not generating a movaps because the vector is aligned to 1.
;CHECK: @foo
;CHECK: xor
;CHECK-NEXT: vmovups
;CHECK-NEXT: ret
define void @foo() {
store <16 x i16> zeroinitializer, <16 x i16>* undef, align 1
ret void
}