RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

[AArch64] Fix ldst-opt of multiple disjunct subregs.

Browse Source 
Currently aarch64-ldst-opt will incorrectly rename registers with
multiple disjunct subregisters (e.g. result of LD3). This patch updates
the canRenameUpToDef to bail out if it encounters such a register class
that contains the register to rename.

Fixes PR46105.

Reviewers: efriedma, dmgreen, paquette, t.p.northover

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D81108
This commit is contained in:
Florian Hahn 2020-06-08 19:25:14 +01:00
parent ef53c559ce
commit 03e283a2c0
2 changed files with 22 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
View File

@ -1287,7 +1287,23 @@ canRenameUpToDef(MachineInstr &FirstMI, LiveRegUnits &UsedInBetween,
LLVM_DEBUG(dbgs() << " Operand not killed at " << FirstMI << "\n"); LLVM_DEBUG(dbgs() << " Operand not killed at " << FirstMI << "\n");
return false; return false;
} }
auto canRenameMOP = [](const MachineOperand &MOP) { auto canRenameMOP = [TRI](const MachineOperand &MOP) {
if (MOP.isReg()) {
auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg());
// Renaming registers with multiple disjunct sub-registers (e.g. the
// result of a LD3) means that all sub-registers are renamed, potentially
// impacting other instructions we did not check. Bail out.
// Note that this relies on the structure of the AArch64 register file. In
// particular, a subregister cannot be written without overwriting the
// whole register.
if (RegClass->HasDisjunctSubRegs) {
LLVM_DEBUG(
dbgs()
<< " Cannot rename operands with multiple disjunct subregisters ("
<< MOP << ")\n");
return false;
}
}
return MOP.isImplicit() || return MOP.isImplicit() ||
(MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied()); (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());
}; };

10
test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
View File

@ -1,5 +1,4 @@
# XFAIL: * # RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -o - -verify-machineinstrs %s | FileCheck %s
# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -verify-machineinstrs -o - %s | FileCheck %s
--- | --- |
define void @test_ld3(<8 x i8>* %a1) { define void @test_ld3(<8 x i8>* %a1) {
entry: entry:
@ -11,11 +10,12 @@
--- ---
# CHECK-LABEL: name: test_ld3 # CHECK-LABEL: name: test_ld3
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: renamable $x0, $d1_d2_d3 = LD3Threev8b_POST killed renamable $x0, $xzr # CHECK: renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
# CHECK-NEXT: STPDi renamable $d0, renamable $d1, $fp, -6 :: (store 8) # CHECK-NEXT: STPDi renamable $d0, renamable $d1, $fp, -6 :: (store 8)
# CHECK-NEXT: STURDi renamable $d2, $fp, -32, implicit killed $d0_d1_d2 :: (store 8 into %ir.s1)
# CHECK-NEXT: renamable $d0_d1_d2 = LD3Threev8b killed renamable $x0 :: (load 24 from %ir.a1, align 32) # CHECK-NEXT: renamable $d0_d1_d2 = LD3Threev8b killed renamable $x0 :: (load 24 from %ir.a1, align 32)
# CHECK-NEXT: STPDi $d3, renamable $d0, $fp, -4 :: (store 8 into %ir.s1), (store 8) # CHECK-NEXT: STPDi renamable $d0, renamable $d1, $fp, -3 :: (store 8)
# CHECK-NEXT: STPDi renamable $d1, renamable $d2, $fp, -2 :: (store 8) # CHECK-NEXT: STURDi renamable $d2, $fp, -8, implicit killed $d0_d1_d2 :: (store 8)
# CHECK-NEXT: RET undef $lr # CHECK-NEXT: RET undef $lr
# #
name: test_ld3 name: test_ld3