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- Cleanup some whitespaces.

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- Convert {0,1} and friends into 0b01, which is identical and more consistent.

llvm-svn: 112593
This commit is contained in:
Bill Wendling 2010-08-31 07:50:46 +00:00
parent e930c65b2c
commit 0409e77e99
1 changed files with 101 additions and 102 deletions
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203
lib/Target/ARM/ARMInstrFormats.td
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@ -88,21 +88,21 @@ class Xform16Bit { bit canXformTo16Bit = 1; }
class AddrMode<bits<4> val> { class AddrMode<bits<4> val> {
bits<4> Value = val; bits<4> Value = val;
} }
def AddrModeNone : AddrMode<0>; def AddrModeNone : AddrMode<0>;
def AddrMode1 : AddrMode<1>; def AddrMode1 : AddrMode<1>;
def AddrMode2 : AddrMode<2>; def AddrMode2 : AddrMode<2>;
def AddrMode3 : AddrMode<3>; def AddrMode3 : AddrMode<3>;
def AddrMode4 : AddrMode<4>; def AddrMode4 : AddrMode<4>;
def AddrMode5 : AddrMode<5>; def AddrMode5 : AddrMode<5>;
def AddrMode6 : AddrMode<6>; def AddrMode6 : AddrMode<6>;
def AddrModeT1_1 : AddrMode<7>; def AddrModeT1_1 : AddrMode<7>;
def AddrModeT1_2 : AddrMode<8>; def AddrModeT1_2 : AddrMode<8>;
def AddrModeT1_4 : AddrMode<9>; def AddrModeT1_4 : AddrMode<9>;
def AddrModeT1_s : AddrMode<10>; def AddrModeT1_s : AddrMode<10>;
def AddrModeT2_i12: AddrMode<11>; def AddrModeT2_i12 : AddrMode<11>;
def AddrModeT2_i8 : AddrMode<12>; def AddrModeT2_i8 : AddrMode<12>;
def AddrModeT2_so : AddrMode<13>; def AddrModeT2_so : AddrMode<13>;
def AddrModeT2_pc : AddrMode<14>; def AddrModeT2_pc : AddrMode<14>;
def AddrModeT2_i8s4 : AddrMode<15>; def AddrModeT2_i8s4 : AddrMode<15>;
// Instruction size. // Instruction size.
@ -247,6 +247,7 @@ class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
let Pattern = pattern; let Pattern = pattern;
list<Predicate> Predicates = [IsARM]; list<Predicate> Predicates = [IsARM];
} }
// A few are not predicable // A few are not predicable
class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz, class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, InstrItinClass itin, IndexMode im, Format f, InstrItinClass itin,
@ -329,16 +330,14 @@ class JTI<dag oops, dag iops, InstrItinClass itin,
: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin, : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
asm, "", pattern>; asm, "", pattern>;
// Atomic load/store instructions // Atomic load/store instructions
class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
opc, asm, "", pattern> { opc, asm, "", pattern> {
let Inst{27-23} = 0b00011; let Inst{27-23} = 0b00011;
let Inst{22-21} = opcod; let Inst{22-21} = opcod;
let Inst{20} = 1; let Inst{20} = 1;
let Inst{11-0} = 0b111110011111; let Inst{11-0} = 0b111110011111;
} }
class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
@ -347,7 +346,7 @@ class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
opc, asm, "", pattern> { opc, asm, "", pattern> {
let Inst{27-23} = 0b00011; let Inst{27-23} = 0b00011;
let Inst{22-21} = opcod; let Inst{22-21} = opcod;
let Inst{20} = 0; let Inst{20} = 0;
let Inst{11-4} = 0b11111001; let Inst{11-4} = 0b11111001;
} }
@ -357,21 +356,21 @@ class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
: I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> { opc, asm, "", pattern> {
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
let Inst{27-26} = {0,0}; let Inst{27-26} = 0b00;
} }
class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> { opc, asm, "", pattern> {
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
let Inst{27-26} = {0,0}; let Inst{27-26} = 0b00;
} }
class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin, class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin, : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> { asm, "", pattern> {
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
let Inst{27-26} = {0,0}; let Inst{27-26} = 0b00;
} }
class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin, class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
@ -384,7 +383,7 @@ class AI2<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin, : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> { opc, asm, "", pattern> {
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// loads // loads
@ -396,7 +395,7 @@ class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin, class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern> string asm, list<dag> pattern>
@ -406,7 +405,7 @@ class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
@ -416,7 +415,7 @@ class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin, class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern> string asm, list<dag> pattern>
@ -426,7 +425,7 @@ class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// stores // stores
@ -438,7 +437,7 @@ class AI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin, class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern> string asm, list<dag> pattern>
@ -448,7 +447,7 @@ class AXI2stw<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin, class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern> string opc, string asm, list<dag> pattern>
@ -458,7 +457,7 @@ class AI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin, class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern> string asm, list<dag> pattern>
@ -468,7 +467,7 @@ class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// Pre-indexed loads // Pre-indexed loads
@ -480,7 +479,7 @@ class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin, class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern> string opc, string asm, string cstr, list<dag> pattern>
@ -490,7 +489,7 @@ class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// Pre-indexed stores // Pre-indexed stores
@ -502,7 +501,7 @@ class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin, class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern> string opc, string asm, string cstr, list<dag> pattern>
@ -512,7 +511,7 @@ class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// Post-indexed loads // Post-indexed loads
@ -524,7 +523,7 @@ class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin, class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern> string opc, string asm, string cstr, list<dag> pattern>
@ -534,7 +533,7 @@ class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// Post-indexed stores // Post-indexed stores
@ -546,7 +545,7 @@ class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 0; // B bit let Inst{22} = 0; // B bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin, class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern> string opc, string asm, string cstr, list<dag> pattern>
@ -556,7 +555,7 @@ class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{22} = 1; // B bit let Inst{22} = 1; // B bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = 0b01;
} }
// addrmode3 instructions // addrmode3 instructions
@ -984,7 +983,7 @@ class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
Encoding { Encoding {
let Inst{31-27} = opcod1; let Inst{31-27} = opcod1;
let Inst{15-14} = opcod2; let Inst{15-14} = opcod2;
let Inst{12} = opcod3; let Inst{12} = opcod3;
} }
// BR_JT instructions // BR_JT instructions
@ -1106,13 +1105,13 @@ class T1Special<bits<4> opcode> : Encoding16 {
// A6.2.4 Load/store single data item encoding. // A6.2.4 Load/store single data item encoding.
class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 { class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
let Inst{15-12} = opA; let Inst{15-12} = opA;
let Inst{11-9} = opB; let Inst{11-9} = opB;
} }
class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>; class T1LdSt<bits<3> opB> : T1LoadStore<0b0101, opB>;
class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes class T1LdSt4Imm<bits<3> opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes
class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte class T1LdSt1Imm<bits<3> opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte
class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
// A6.2.5 Miscellaneous 16-bit instructions encoding. // A6.2.5 Miscellaneous 16-bit instructions encoding.
class T1Misc<bits<7> opcode> : Encoding16 { class T1Misc<bits<7> opcode> : Encoding16 {
@ -1132,9 +1131,10 @@ class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
list<Predicate> Predicates = [IsThumb2]; list<Predicate> Predicates = [IsThumb2];
} }
// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
// an input operand since by default it's a zero register. It will // input operand since by default it's a zero register. It will become an
// become an implicit def once it's "flipped". // implicit def once it's "flipped".
//
// FIXME: This uses unified syntax so {s} comes before {p}. We should make it // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
// more consistent. // more consistent.
class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz, class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
@ -1192,11 +1192,11 @@ class T2Ii8s4<bit P, bit W, bit load, dag oops, dag iops, InstrItinClass itin,
pattern> { pattern> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24} = P; let Inst{24} = P;
let Inst{23} = ?; // The U bit. let Inst{23} = ?; // The U bit.
let Inst{22} = 1; let Inst{22} = 1;
let Inst{21} = W; let Inst{21} = W;
let Inst{20} = load; let Inst{20} = load;
} }
class T2sI<dag oops, dag iops, InstrItinClass itin, class T2sI<dag oops, dag iops, InstrItinClass itin,
@ -1232,14 +1232,14 @@ class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
list<Predicate> Predicates = [IsThumb2]; list<Predicate> Predicates = [IsThumb2];
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
let Inst{24} = signed; let Inst{24} = signed;
let Inst{23} = 0; let Inst{23} = 0;
let Inst{22-21} = opcod; let Inst{22-21} = opcod;
let Inst{20} = load; let Inst{20} = load;
let Inst{11} = 1; let Inst{11} = 1;
// (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
let Inst{10} = pre; // The P bit. let Inst{10} = pre; // The P bit.
let Inst{8} = 1; // The W bit. let Inst{8} = 1; // The W bit.
} }
// Helper class for disassembly only // Helper class for disassembly only
@ -1250,9 +1250,9 @@ class T2I_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, dag iops,
: T2I<oops, iops, itin, opc, asm, pattern> { : T2I<oops, iops, itin, opc, asm, pattern> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-24} = 0b011; let Inst{26-24} = 0b011;
let Inst{23} = long; let Inst{23} = long;
let Inst{22-20} = op22_20; let Inst{22-20} = op22_20;
let Inst{7-4} = op7_4; let Inst{7-4} = op7_4;
} }
// Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
@ -1374,8 +1374,8 @@ class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
let Inst{27-23} = opcod1; let Inst{27-23} = opcod1;
let Inst{21-20} = opcod2; let Inst{21-20} = opcod2;
let Inst{11-8} = 0b1011; let Inst{11-8} = 0b1011;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// Double precision, binary, VML[AS] (for additional predicate) // Double precision, binary, VML[AS] (for additional predicate)
@ -1386,12 +1386,11 @@ class ADbI_vmlX<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
let Inst{27-23} = opcod1; let Inst{27-23} = opcod1;
let Inst{21-20} = opcod2; let Inst{21-20} = opcod2;
let Inst{11-8} = 0b1011; let Inst{11-8} = 0b1011;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
list<Predicate> Predicates = [HasVFP2, UseVMLx]; list<Predicate> Predicates = [HasVFP2, UseVMLx];
} }
// Single precision, unary // Single precision, unary
class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
@ -1422,8 +1421,8 @@ class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
let Inst{27-23} = opcod1; let Inst{27-23} = opcod1;
let Inst{21-20} = opcod2; let Inst{21-20} = opcod2;
let Inst{11-8} = 0b1010; let Inst{11-8} = 0b1010;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// Single precision binary, if no NEON // Single precision binary, if no NEON
@ -1528,10 +1527,10 @@ class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
: NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm, : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
cstr, pattern> { cstr, pattern> {
let Inst{31-24} = 0b11110100; let Inst{31-24} = 0b11110100;
let Inst{23} = op23; let Inst{23} = op23;
let Inst{21-20} = op21_20; let Inst{21-20} = op21_20;
let Inst{11-8} = op11_8; let Inst{11-8} = op11_8;
let Inst{7-4} = op7_4; let Inst{7-4} = op7_4;
} }
class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr> class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
@ -1563,13 +1562,13 @@ class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
string opc, string dt, string asm, string cstr, string opc, string dt, string asm, string cstr,
list<dag> pattern> list<dag> pattern>
: NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> { : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
let Inst{23} = op23; let Inst{23} = op23;
let Inst{21-19} = op21_19; let Inst{21-19} = op21_19;
let Inst{11-8} = op11_8; let Inst{11-8} = op11_8;
let Inst{7} = op7; let Inst{7} = op7;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{5} = op5; let Inst{5} = op5;
let Inst{4} = op4; let Inst{4} = op4;
} }
// NEON 2 vector register format. // NEON 2 vector register format.
@ -1582,9 +1581,9 @@ class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
let Inst{21-20} = op21_20; let Inst{21-20} = op21_20;
let Inst{19-18} = op19_18; let Inst{19-18} = op19_18;
let Inst{17-16} = op17_16; let Inst{17-16} = op17_16;
let Inst{11-7} = op11_7; let Inst{11-7} = op11_7;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// Same as N2V except it doesn't have a datatype suffix. // Same as N2V except it doesn't have a datatype suffix.
@ -1597,9 +1596,9 @@ class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
let Inst{21-20} = op21_20; let Inst{21-20} = op21_20;
let Inst{19-18} = op19_18; let Inst{19-18} = op19_18;
let Inst{17-16} = op17_16; let Inst{17-16} = op17_16;
let Inst{11-7} = op11_7; let Inst{11-7} = op11_7;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// NEON 2 vector register with immediate. // NEON 2 vector register with immediate.
@ -1607,12 +1606,12 @@ class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
dag oops, dag iops, Format f, InstrItinClass itin, dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string dt, string asm, string cstr, list<dag> pattern> string opc, string dt, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
let Inst{24} = op24; let Inst{24} = op24;
let Inst{23} = op23; let Inst{23} = op23;
let Inst{11-8} = op11_8; let Inst{11-8} = op11_8;
let Inst{7} = op7; let Inst{7} = op7;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// NEON 3 vector register format. // NEON 3 vector register format.
@ -1620,12 +1619,12 @@ class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
dag oops, dag iops, Format f, InstrItinClass itin, dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string dt, string asm, string cstr, list<dag> pattern> string opc, string dt, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> { : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
let Inst{24} = op24; let Inst{24} = op24;
let Inst{23} = op23; let Inst{23} = op23;
let Inst{21-20} = op21_20; let Inst{21-20} = op21_20;
let Inst{11-8} = op11_8; let Inst{11-8} = op11_8;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// Same as N3V except it doesn't have a data type suffix. // Same as N3V except it doesn't have a data type suffix.
@ -1634,12 +1633,12 @@ class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
dag oops, dag iops, Format f, InstrItinClass itin, dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern> string opc, string asm, string cstr, list<dag> pattern>
: NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> { : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
let Inst{24} = op24; let Inst{24} = op24;
let Inst{23} = op23; let Inst{23} = op23;
let Inst{21-20} = op21_20; let Inst{21-20} = op21_20;
let Inst{11-8} = op11_8; let Inst{11-8} = op11_8;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = op4; let Inst{4} = op4;
} }
// NEON VMOVs between scalar and core registers. // NEON VMOVs between scalar and core registers.
@ -1649,9 +1648,9 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
: InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain, : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
"", itin> { "", itin> {
let Inst{27-20} = opcod1; let Inst{27-20} = opcod1;
let Inst{11-8} = opcod2; let Inst{11-8} = opcod2;
let Inst{6-5} = opcod3; let Inst{6-5} = opcod3;
let Inst{4} = 1; let Inst{4} = 1;
let OutOperandList = oops; let OutOperandList = oops;
let InOperandList = !con(iops, (ins pred:$p)); let InOperandList = !con(iops, (ins pred:$p));
@ -1685,9 +1684,9 @@ class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
let Inst{24-23} = 0b11; let Inst{24-23} = 0b11;
let Inst{21-20} = 0b11; let Inst{21-20} = 0b11;
let Inst{19-16} = op19_16; let Inst{19-16} = op19_16;
let Inst{11-7} = 0b11000; let Inst{11-7} = 0b11000;
let Inst{6} = op6; let Inst{6} = op6;
let Inst{4} = 0; let Inst{4} = 0;
} }
// NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON