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[Sparc] Add support to decode negative simm13 operands in the sparc disassembler.
llvm-svn: 202578
This commit is contained in:
Venkatraman Govindaraju
parent
fcbe857272
commit
043ff79772
@ -192,6 +192,8 @@ static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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#include "SparcGenDisassemblerTables.inc"
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@ -357,3 +359,10 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
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MI.addOperand(MCOperand::CreateImm(tgt));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
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uint64_t Address, const void *Decoder) {
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unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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MI.addOperand(MCOperand::CreateImm(tgt));
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return MCDisassembler::Success;
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}
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@ -109,6 +109,10 @@ def calltarget : Operand<i32> {
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let DecoderMethod = "DecodeCall";
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}
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def simm13Op : Operand<i32> {
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let DecoderMethod = "DecodeSIMM13";
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}
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// Operand for printing out a condition code.
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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@ -247,7 +251,7 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
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(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
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def ri : F3_2<2, Op3Val,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
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(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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!strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
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}
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@ -433,42 +437,42 @@ let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
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// Section B.11 - Logical Instructions, p. 106
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defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
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defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
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def ANDNrr : F3_1<2, 0b000101,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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"andn $rs1, $rs2, $rd",
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[(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
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def ANDNri : F3_2<2, 0b000101,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
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(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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"andn $rs1, $simm13, $rd", []>;
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defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
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defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
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def ORNrr : F3_1<2, 0b000110,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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"orn $rs1, $rs2, $rd",
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[(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
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def ORNri : F3_2<2, 0b000110,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
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(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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"orn $rs1, $simm13, $rd", []>;
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defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
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defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
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def XNORrr : F3_1<2, 0b000111,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
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"xnor $rs1, $rs2, $rd",
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[(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
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def XNORri : F3_2<2, 0b000111,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
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(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
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"xnor $rs1, $simm13, $rd", []>;
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// Section B.12 - Shift Instructions, p. 107
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defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
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defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
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defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
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defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
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defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
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defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
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// Section B.13 - Add Instructions, p. 108
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defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
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defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
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// "LEA" forms of add (patterns to make tblgen happy)
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let Predicates = [Is32Bit], isCodeGenOnly = 1 in
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@ -478,18 +482,18 @@ let Predicates = [Is32Bit], isCodeGenOnly = 1 in
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[(set iPTR:$dst, ADDRri:$addr)]>;
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let Defs = [ICC] in
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defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
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defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
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let Uses = [ICC], Defs = [ICC] in
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defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
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defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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// Section B.15 - Subtract Instructions, p. 110
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defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
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defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
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let Uses = [ICC], Defs = [ICC] in
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defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
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defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
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let Defs = [ICC] in
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defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
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defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
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let Defs = [ICC], rd = 0 in {
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def CMPrr : F3_1<2, 0b010100,
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@ -497,7 +501,7 @@ let Defs = [ICC], rd = 0 in {
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"cmp $rs1, $rs2",
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[(SPcmpicc i32:$rs1, i32:$rs2)]>;
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def CMPri : F3_2<2, 0b010100,
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(outs), (ins IntRegs:$rs1, i32imm:$simm13),
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(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
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"cmp $rs1, $simm13",
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[(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
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}
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@ -505,7 +509,7 @@ let Defs = [ICC], rd = 0 in {
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// Section B.18 - Multiply Instructions, p. 113
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let Defs = [Y] in {
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defm UMUL : F3_12np<"umul", 0b001010>;
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defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
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defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
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}
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// Section B.19 - Divide Instructions, p. 115
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@ -607,11 +611,11 @@ let Uses = [Y], rs1 = 0, rs2 = 0 in
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// Section B.29 - Write State Register Instructions
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let Defs = [Y], rd = 0 in {
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def WRYrr : F3_1<2, 0b110000,
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(outs), (ins IntRegs:$b, IntRegs:$c),
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"wr $b, $c, %y", []>;
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(outs), (ins IntRegs:$rs1, IntRegs:$rs2),
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"wr $rs1, $rs2, %y", []>;
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def WRYri : F3_2<2, 0b110000,
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(outs), (ins IntRegs:$b, i32imm:$c),
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"wr $b, $c, %y", []>;
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(outs), (ins IntRegs:$rs1, simm13Op:$simm13),
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"wr $rs1, $simm13, %y", []>;
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}
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3u<2, 0b110100, 0b011000100,
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@ -946,7 +950,7 @@ let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
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def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
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let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
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def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
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def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
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"membar $simm13", []>;
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let Constraints = "$val = $dst" in {
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@ -173,3 +173,16 @@
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# CHECK: call 16
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0x40 0x00 0x00 0x04
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# CHECK: add %g1, -10, %g2
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0x84 0x00 0x7f 0xf6
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# CHECK: save %sp, -196, %sp
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0x9d 0xe3 0xbf 0x3c
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# CHECK: cmp %g1, -2
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0x80 0xa0 0x7f 0xfe
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# CHECK: wr %g1, -2, %y
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0x81 0x80 0x7f 0xfe
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