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[PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

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This patch implements builtins for the following prototypes:
```
vector signed char vec_clrl (vector signed char a, unsigned int n);
vector unsigned char vec_clrl (vector unsigned char a, unsigned int n);
vector signed char vec_clrr (vector signed char a, unsigned int n);
vector signed char vec_clrr (vector unsigned char a, unsigned int n);
```

Differential Revision: https://reviews.llvm.org/D81707
This commit is contained in:
Amy Kwan 2020-06-20 18:29:16 -05:00
parent 60377c3da8
commit 048b03aa1b
5 changed files with 57 additions and 0 deletions
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8
include/llvm/IR/IntrinsicsPowerPC.td
View File

@ -417,6 +417,14 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
def int_ppc_altivec_vpextd : GCCBuiltin<"__builtin_altivec_vpextd">,
Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem]>;
// P10 Vector Clear Bytes
def int_ppc_altivec_vclrlb : GCCBuiltin<"__builtin_altivec_vclrlb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem]>;
def int_ppc_altivec_vclrrb : GCCBuiltin<"__builtin_altivec_vclrrb">,
Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
[IntrNoMem]>;
}
// Vector average.

8
lib/Target/PowerPC/PPCInstrPrefix.td
View File

@ -516,4 +516,12 @@ let Predicates = [IsISA3_1] in {
def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"pextd $rA, $rS, $rB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
"vclrlb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD,
(int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
"vclrrb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
}

29
test/CodeGen/PowerPC/p10-string-ops.ll Normal file
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@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; These test cases aim to test the vector string isolate builtins on Power10.
declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)
declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)
define <16 x i8> @test_vclrlb(<16 x i8> %a, i32 %n) {
; CHECK-LABEL: test_vclrlb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vclrlb v2, v2, r5
; CHECK-NEXT: blr
entry:
%tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8> %a, i32 %n)
ret <16 x i8> %tmp
}
define <16 x i8> @test_vclrrb(<16 x i8> %a, i32 %n) {
; CHECK-LABEL: test_vclrrb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vclrrb v2, v2, r5
; CHECK-NEXT: blr
entry:
%tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)
ret <16 x i8> %tmp
}

6
test/MC/Disassembler/PowerPC/p10insts.txt
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@ -12,3 +12,9 @@
# CHECK: pextd 1, 2, 4
0x7c 0x41 0x21 0x78
# CHECK: vclrlb 1, 4, 3
0x10 0x24 0x19 0x8d
# CHECK: vclrrb 1, 4, 3
0x10 0x24 0x19 0xcd

6
test/MC/PowerPC/p10.s
View File

@ -15,3 +15,9 @@
# CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
# CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
pextd 1, 2, 4
# CHECK-BE: vclrlb 1, 4, 3 # encoding: [0x10,0x24,0x19,0x8d]
# CHECK-LE: vclrlb 1, 4, 3 # encoding: [0x8d,0x19,0x24,0x10]
vclrlb 1, 4, 3
# CHECK-BE: vclrrb 1, 4, 3 # encoding: [0x10,0x24,0x19,0xcd]
# CHECK-LE: vclrrb 1, 4, 3 # encoding: [0xcd,0x19,0x24,0x10]
vclrrb 1, 4, 3