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[PowerPC] Add support for llvm.ppc.dcbt, llvm.ppc.dcbtst, llvm.ppc.isync intrinsics

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This patch adds LLVM intrinsics for the dcbt (Data Cache Block Touch),
dcbtst (Data Cache Block Touch for Store) and isync (Instruction
Synchronize) instructions.

The intrinsic for dcbt and dcbst in this patch are named llvm.ppc.dcbt.with.hint
and llvm.ppc.dcbtst.with.hint respectively as there already exists an intrinsic
for llvm.ppc.dcbt and llvm.ppc.dcbtst. However, the original variants of the
intrinsics do not accept the TH immediate field, whereas these variants do.

Differential Revision: https://reviews.llvm.org/D79633
This commit is contained in:
Amy Kwan 2020-06-26 12:22:38 -05:00
parent 14ba3c75bf
commit 04ae1ab1c3
4 changed files with 96 additions and 0 deletions
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6
include/llvm/IR/IntrinsicsPowerPC.td
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@ -28,6 +28,10 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
[IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
def int_ppc_dcbt_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
[IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
def int_ppc_dcbtst_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
[IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
@ -36,6 +40,8 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
// sync instruction (i.e. sync 0, a.k.a hwsync)
def int_ppc_sync : Intrinsic<[], [], []>;
// isync instruction
def int_ppc_isync : Intrinsic<[], [], []>;
// lwsync is sync 1
def int_ppc_lwsync : Intrinsic<[], [], []>;
// eieio instruction

6
lib/Target/PowerPC/PPCInstrInfo.td
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@ -1835,6 +1835,11 @@ def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
(ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH),
(DCBT i32:$TH, xoaddr:$dst)>;
def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH),
(DCBTST i32:$TH, xoaddr:$dst)>;
// Atomic operations
// FIXME: some of these might be used with constant operands. This will result
// in constant materialization instructions that may be redundant. We currently
@ -4506,6 +4511,7 @@ def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
def : Pat<(int_ppc_isync), (ISYNC)>;
def : Pat<(int_ppc_dcbfl xoaddr:$dst),
(DCBF 1, xoaddr:$dst)>;
def : Pat<(int_ppc_dcbflp xoaddr:$dst),

67
test/CodeGen/PowerPC/dcbt.ll Normal file
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@ -0,0 +1,67 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr | FileCheck %s
define void @dcbt_with_hint_test1(i8* %a) {
; CHECK-LABEL: dcbt_with_hint_test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dcbt 0, r3
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 0)
ret void
}
define void @dcbt_with_hint_test2(i8* %a) {
; CHECK-LABEL: dcbt_with_hint_test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dcbt 0, r3, 8
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 8)
ret void
}
define void @dcbt_with_hint_test3(i8* %a) {
; CHECK-LABEL: dcbt_with_hint_test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dcbt 0, r3, 15
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 15)
ret void
}
define void @dcbtst_with_hint_test1(i8* %a) {
; CHECK-LABEL: dcbtst_with_hint_test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dcbtst 0, r3
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 0)
ret void
}
define void @dcbtst_with_hint_test2(i8* %a) {
; CHECK-LABEL: dcbtst_with_hint_test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dcbtst 0, r3, 8
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 8)
ret void
}
define void @dcbtst_with_hint_test3(i8* %a) {
; CHECK-LABEL: dcbtst_with_hint_test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dcbtst 0, r3, 15
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 15)
ret void
}
declare void @llvm.ppc.dcbt.with.hint(i8*, i32)
declare void @llvm.ppc.dcbtst.with.hint(i8*, i32)

17
test/CodeGen/PowerPC/isync.ll Normal file
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@ -0,0 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr | FileCheck %s
define void @isync_test() {
; CHECK-LABEL: isync_test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: isync
; CHECK-NEXT: blr
entry:
tail call void @llvm.ppc.isync()
ret void
}
declare void @llvm.ppc.isync()