diff --git a/lib/Target/PowerPC/PPC32ISelPattern.cpp b/lib/Target/PowerPC/PPC32ISelPattern.cpp
index de87667b634..50b10e41f14 100644
--- a/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -811,7 +811,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
   default:
     Node->dump(); std::cerr << '\n';
     assert(0 && "Node not handled!\n");
-  case ISD::BUILTIN_OP_END+PPC::FSEL:
+  case PPCISD::FSEL:
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
     Tmp3 = SelectExpr(N.getOperand(2));
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 8c0d6d00bec..934f811fb14 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -629,7 +629,8 @@ SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
 // target-specific node if it hasn't already been changed.
 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
-  if (N->getOpcode() >= ISD::BUILTIN_OP_END)
+  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
+      N->getOpcode() < PPCISD::FIRST_NUMBER)
     return Op;   // Already selected.
   
   switch (N->getOpcode()) {
@@ -747,6 +748,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     assert(N->getValueType(0) == MVT::i32);
     CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
     break;
+  case PPCISD::FSEL:
+    CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
+                         Select(N->getOperand(0)),
+                         Select(N->getOperand(1)),
+                         Select(N->getOperand(2)));
+    break;
   case ISD::ADD: {
     MVT::ValueType Ty = N->getValueType(0);
     if (Ty == MVT::i32) {
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 7d46477b339..d84552c5c0a 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -125,34 +125,34 @@ SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
           std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
         case ISD::SETUGE:
         case ISD::SETGE:
-          return DAG.getTargetNode(PPC::FSEL, ResVT, LHS, TV, FV);
+          return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
         case ISD::SETUGT:
         case ISD::SETGT:
           std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
         case ISD::SETULE:
         case ISD::SETLE:
-          return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                   DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
+          return DAG.getNode(PPCISD::FSEL, ResVT,
+                             DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
         }
       
       switch (CC) {
       default: assert(0 && "Invalid FSEL condition"); abort();
       case ISD::SETULT:
       case ISD::SETLT:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV,TV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
       case ISD::SETUGE:
       case ISD::SETGE:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV,FV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
       case ISD::SETUGT:
       case ISD::SETGT:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV,TV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
       case ISD::SETULE:
       case ISD::SETLE:
-        return DAG.getTargetNode(PPC::FSEL, ResVT,
-                                 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV,FV);
+        return DAG.getNode(PPCISD::FSEL, ResVT,
+                           DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
       }
     }
     break;    
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index aa01934aa1e..b2dd4daedde 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -1,4 +1,4 @@
-//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Impl. --------*- C++ -*-===//
+//===-- PPC32ISelLowering.h - PPC32 DAG Lowering Interface ------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -16,8 +16,21 @@
 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
 
 #include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "PowerPC.h"
 
 namespace llvm {
+  namespace PPCISD {
+    enum NodeType {
+      // Start the numbering where the builting ops and target ops leave off.
+      FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
+
+      /// FSEL - Traditional three-operand fsel node.
+      ///
+      FSEL,
+    };
+  }  
+  
   class PPC32TargetLowering : public TargetLowering {
     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
     int ReturnAddrIndex;              // FrameIndex for return slot.