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[CostModel] Return Invalid cost in getArithmeticCost instead of crashing for scalable vectors.

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This fixes an issue in BasicTTIImpl.h where it tries to do a
cast<FixedVectorType> on a scalable vector type in order to get the
scalarization cost. Because scalarization of scalable vectors is not
supported, we return Invalid instead.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103798
This commit is contained in:
Sander de Smalen 2021-06-07 13:02:38 +01:00
parent 1d2a2e625f
commit 052444882c
2 changed files with 68 additions and 3 deletions
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10
include/llvm/CodeGen/BasicTTIImpl.h
View File

@ -776,18 +776,22 @@ public:
return LT.first * 2 * OpCost;
}
// We cannot scalarize scalable vectors, so return Invalid.
if (isa<ScalableVectorType>(Ty))
return InstructionCost::getInvalid();
// Else, assume that we need to scalarize this op.
// TODO: If one of the types get legalized by splitting, handle this
// similarly to what getCastInstrCost() does.
if (auto *VTy = dyn_cast<VectorType>(Ty)) {
unsigned Num = cast<FixedVectorType>(VTy)->getNumElements();
if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) {
InstructionCost Cost = thisT()->getArithmeticInstrCost(
Opcode, VTy->getScalarType(), CostKind, Opd1Info, Opd2Info,
Opd1PropInfo, Opd2PropInfo, Args, CxtI);
// Return the cost of multiple scalar invocation plus the cost of
// inserting and extracting the values.
SmallVector<Type *> Tys(Args.size(), Ty);
return getScalarizationOverhead(VTy, Args, Tys) + Num * Cost;
return getScalarizationOverhead(VTy, Args, Tys) +
VTy->getNumElements() * Cost;
}
// We don't know anything about this scalar instruction.

61
test/Analysis/CostModel/AArch64/sve-remainder.ll Normal file
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@ -0,0 +1,61 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt -cost-model -analyze -mtriple aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
define void @test_urem_srem_expand() {
; CHECK-LABEL: 'test_urem_srem_expand'
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_urem_0 = urem <vscale x 32 x i8> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_urem_1 = urem <vscale x 16 x i16> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_urem_2 = urem <vscale x 8 x i32> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_urem_3 = urem <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_srem_0 = srem <vscale x 32 x i8> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_srem_1 = srem <vscale x 16 x i16> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_srem_2 = srem <vscale x 8 x i32> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %split_type_srem_3 = srem <vscale x 4 x i64> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef
; CHECK-NEXT: Cost Model: Invalid cost for instruction: %widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
entry:
%legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef
%legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef
%legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef
%legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef
%legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef
%legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef
%legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef
%legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef
%split_type_urem_0 = urem <vscale x 32 x i8> undef, undef
%split_type_urem_1 = urem <vscale x 16 x i16> undef, undef
%split_type_urem_2 = urem <vscale x 8 x i32> undef, undef
%split_type_urem_3 = urem <vscale x 4 x i64> undef, undef
%split_type_srem_0 = srem <vscale x 32 x i8> undef, undef
%split_type_srem_1 = srem <vscale x 16 x i16> undef, undef
%split_type_srem_2 = srem <vscale x 8 x i32> undef, undef
%split_type_srem_3 = srem <vscale x 4 x i64> undef, undef
%widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef
%widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef
%widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef
%widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef
%widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef
%widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef
%widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef
%widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef
ret void
}